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mti_CreateProcess()

Creates a new VHDL process.

Syntax 

process_id = mti_CreateProcess( name, func, param )

Returns

Name
Type
Description
process_id
mtiProcessIdT
A handle to the new VHDL process or NULL if there is an error

Arguments

Name
Type
Description
name
char *
The name of the new VHDL process; OPTIONAL - can be NULL
func
mtiVoidFuncPtrT
A pointer to the function that will be executed as the body of the new process
param
void *
A parameter to be passed to the function; OPTIONAL - can be NULL

Description

mti_CreateProcess() creates a new VHDL process with the specified name. If the name is non-NULL, then it appears in the simulator's Process window; otherwise, it does not. The specified function is called along with its parameter whenever the process executes. The process executes either at the time specified in a call to mti_ScheduleWakeup() or whenever one of the signals to which it is sensitive changes (see mti_Sensitize()).

If the process is created during elaboration from inside of a foreign architecture instance, then the process is automatically executed once at time zero after all signals have been initialized. If the process is created either after elaboration is complete or from any other context (such as from an initialization function that executes as a result of the loading of a foreign shared library by the -foreign option to vsim), then the process is not run automatically but must be scheduled or sensitized.

Related functions

mti_CreateProcessWithPriority()

mti_Desensitize()

mti_GetProcessName()

mti_ScheduleWakeup()

mti_Sensitize()

Example

FLI code 

#include <stdlib.h>
#include <mti.h>

typedef enum {
  STD_LOGIC_U,
  STD_LOGIC_X,
  STD_LOGIC_0,
  STD_LOGIC_1,
  STD_LOGIC_Z,
  STD_LOGIC_W,
  STD_LOGIC_L,
  STD_LOGIC_H,
  STD_LOGIC_D
} standardLogicType;

typedef struct {
  mtiSignalIdT sigid;
  mtiDriverIdT drvid;
} instanceInfoT;

char * convertStdLogicValue( mtiInt32T sigval )
{
  char * retval;

  switch ( sigval ) {
    case STD_LOGIC_U:  retval = "'U'";  break;
    case STD_LOGIC_X:  retval = "'X'";  break;
    case STD_LOGIC_0:  retval = "'0'";  break;
    case STD_LOGIC_1:  retval = "'1'";  break;
    case STD_LOGIC_Z:  retval = "'Z'";  break;
    case STD_LOGIC_W:  retval = "'W'";  break;
    case STD_LOGIC_L:  retval = "'L'";  break;
    case STD_LOGIC_H:  retval = "'H'";  break;
    case STD_LOGIC_D:  retval = "'-'";  break;
    default:  retval = "?";  break;
  }
  return retval;
}

void driveSignal( void * param )
{
  char          * region_name;
  instanceInfoT * inst = (instanceInfoT*)param;
  mtiInt32T       sigval;

  region_name = mti_GetRegionFullName(mti_GetSignalRegion(inst->sigid));   sigval = mti_GetSignalValue( inst->sigid );
  mti_PrintFormatted( "Time [%d,%d] delta %d: Signal %s/%s is %s\n",
                     mti_NowUpper(), mti_Now(), mti_Delta(),
                     region_name, mti_GetSignalName( inst->sigid ),
                     convertStdLogicValue( sigval ) );

  switch ( sigval ) {
    case STD_LOGIC_U:  sigval = STD_LOGIC_X;  break;
    case STD_LOGIC_X:  sigval = STD_LOGIC_0;  break;
    case STD_LOGIC_0:  sigval = STD_LOGIC_1;  break;
    case STD_LOGIC_1:  sigval = STD_LOGIC_Z;  break;
    case STD_LOGIC_Z:  sigval = STD_LOGIC_W;  break;
    case STD_LOGIC_W:  sigval = STD_LOGIC_L;  break;
    case STD_LOGIC_L:  sigval = STD_LOGIC_H;  break;
    case STD_LOGIC_H:  sigval = STD_LOGIC_D;  break;
    case STD_LOGIC_D:  sigval = STD_LOGIC_U;  break;
    default:  sigval = STD_LOGIC_U;  break;
  }
  mti_ScheduleDriver( inst->drvid, sigval, 5, MTI_INERTIAL );

  mti_VsimFree( region_name );
}

void cleanupCallback( void * param )
{
  mti_PrintMessage( "Cleaning up...\n" );
  free( param );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  instanceInfoT * inst;
  mtiProcessIdT   procid;

  inst        = (instanceInfoT *)malloc( sizeof(instanceInfoT) );
  inst->sigid = mti_FindSignal( "/top/s1" );
  inst->drvid = mti_CreateDriver( inst->sigid );
  procid      = mti_CreateProcess( "sigDriver", driveSignal, inst );
  mti_Sensitize( procid, inst->sigid, MTI_EVENT );
  mti_SetDriverOwner( inst->drvid, procid );
  mti_AddQuitCB( cleanupCallback, inst );
  mti_AddRestartCB( cleanupCallback, inst );
}

HDL code 

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a;

library ieee;
use ieee.std_logic_1164.all;

entity top is
end top;

architecture a of top is

  signal s1 : std_logic := '0';

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

begin

  i1 : for_model;

end a;

Simulation output 

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
VSIM 1> run 50 
# Time [0,0] delta 0: Signal /top/s1 is '0'
# Time [0,5] delta 0: Signal /top/s1 is '1'
# Time [0,10] delta 0: Signal /top/s1 is 'Z'
# Time [0,15] delta 0: Signal /top/s1 is 'W'
# Time [0,20] delta 0: Signal /top/s1 is 'L'
# Time [0,25] delta 0: Signal /top/s1 is 'H'
# Time [0,30] delta 0: Signal /top/s1 is '-'
# Time [0,35] delta 0: Signal /top/s1 is 'U'
# Time [0,40] delta 0: Signal /top/s1 is 'X'
# Time [0,45] delta 0: Signal /top/s1 is '0'
# Time [0,50] delta 0: Signal /top/s1 is '1'
VSIM 2> quit
# Cleaning up...

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