mti_ScheduleDriver()

Model Technology Inc.

mti_ScheduleDriver()

Schedules a driver to drive a value onto a VHDL signal.

Syntax

mti_ScheduleDriver( driver_id, value, delay, mode )

Returns

Nothing

Arguments


Name	Type	Description
driver	mtiDriverIdT	A handle to the driver
value	long/void *	For a signal of scalar type, the value to be driven; for a signal of real, time, or array type, a pointer to the value to be driven
delay	mtiDelayT	The delay to be used in current simulator time units
mode	mtiDriverModeT	Indicates either inertial or transport delay

Description

mti_ScheduleDriver() schedules a transaction on the specified driver. If the signal being driven is of an array, real, or time type, then the value type is considered to be "void *" instead of "long". The delay time units are equivalent to the current simulator time unit setting. The mode parameter can be either MTI_INERTIAL or MTI_TRANSPORT.

Related functions

mti_CreateDriver()

mti_ForceSignal()

mti_GetResolutionLimit()

mti_SetSignalValue()

Example

FLI code

#include <stdlib.h>
#include <mti.h>

typedef enum {
  STD_LOGIC_U,
  STD_LOGIC_X,
  STD_LOGIC_0,
  STD_LOGIC_1,
  STD_LOGIC_Z,
  STD_LOGIC_W,
  STD_LOGIC_L,
  STD_LOGIC_H,
  STD_LOGIC_D
} StdLogicType;

typedef struct {
  mtiDelayT     delay;
  mtiProcessIdT procid;
  mtiSignalIdT  i1_sigid;
  mtiSignalIdT  i2_sigid;
  mtiSignalIdT  i3_sigid;
  mtiSignalIdT  t1_sigid;
  mtiSignalIdT  t2_sigid;
  mtiSignalIdT  t3_sigid;
  mtiDriverIdT  i1_drvid;
  mtiDriverIdT  i2_drvid;
  mtiDriverIdT  i3_drvid;
  mtiDriverIdT  t1_drvid;
  mtiDriverIdT  t2_drvid;
  mtiDriverIdT  t3_drvid;
  long          i1_last_value;
  long          i2_last_value;
  void *        i3_last_value;
  long          t1_last_value;
  long          t2_last_value;
  void *        t3_last_value;
  mtiInt32T     i3_value_length;
  mtiInt32T     t3_value_length;
} instanceInfoT;

static long invertBit( long value )
{
  if ( value == 0 ) {
    return 1;
  } else {
    return 0;
  }
}

static void invertBitArray( char * value, mtiInt32T length )
{
  int i;
  for ( i = 0; i < length; i++ ) {
    if ( value[i] == 0 ) {
      value[i] = 1;
    } else {
      value[i] = 0;
    }
  }
}

static long incrStdLogic( mtiInt32T value )
{
  switch ( value ) {
    case STD_LOGIC_U:  return STD_LOGIC_X;
    case STD_LOGIC_X:  return STD_LOGIC_0;
    case STD_LOGIC_0:  return STD_LOGIC_1;
    case STD_LOGIC_1:  return STD_LOGIC_Z;
    case STD_LOGIC_Z:  return STD_LOGIC_W;
    case STD_LOGIC_W:  return STD_LOGIC_L;
    case STD_LOGIC_L:  return STD_LOGIC_H;
    case STD_LOGIC_H:  return STD_LOGIC_D;
    case STD_LOGIC_D:  return STD_LOGIC_U;
    default:           return STD_LOGIC_U;
  }
}

void driveSignal( instanceInfoT * inst )
{
 inst->i1_last_value = invertBit( inst->i1_last_value );
 mti_ScheduleDriver( inst->i1_drvid, inst->i1_last_value, 5, MTI_INERTIAL );

 inst->i2_last_value = incrStdLogic( inst->i2_last_value );
 mti_ScheduleDriver( inst->i2_drvid, inst->i2_last_value, 5, MTI_INERTIAL );

 invertBitArray( inst->i3_last_value, inst->i3_value_length );
 mti_ScheduleDriver( inst->i3_drvid, (long)(inst->i3_last_value), 5, MTI_INERTIAL );

 inst->t1_last_value = invertBit( inst->t1_last_value );
 mti_ScheduleDriver( inst->t1_drvid, inst->t1_last_value, 5, MTI_TRANSPORT );

 inst->t2_last_value = incrStdLogic( inst->t2_last_value );
 mti_ScheduleDriver( inst->t2_drvid, inst->t2_last_value, 5, MTI_TRANSPORT );

 invertBitArray( inst->t3_last_value, inst->t3_value_length );
 mti_ScheduleDriver( inst->t3_drvid, (long)(inst->t3_last_value), 5, MTI_TRANSPORT );

 mti_ScheduleWakeup( inst->procid, inst->delay );
 inst->delay++;
}

void cleanupCallback( void * param )
{
  mti_PrintMessage( "Cleaning up...\n" );
  free( param );
}

void loadDoneCallback( instanceInfoT * inst )
{
  inst->i1_last_value   = mti_GetSignalValue( inst->i1_sigid );
  inst->i2_last_value   = mti_GetSignalValue( inst->i2_sigid );
  inst->i3_last_value   = mti_GetArraySignalValue( inst->i3_sigid, 0 );
  inst->i3_value_length = mti_TickLength( mti_GetSignalType(inst->i3_sigid));
  inst->t1_last_value   = mti_GetSignalValue( inst->t1_sigid );
  inst->t2_last_value   = mti_GetSignalValue( inst->t2_sigid );
  inst->t3_last_value   = mti_GetArraySignalValue( inst->t3_sigid, 0 );
  inst->t3_value_length = mti_TickLength( mti_GetSignalType(inst->t3_sigid));
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  instanceInfoT * inst;

  inst = (instanceInfoT *)malloc( sizeof(instanceInfoT) );

  inst->procid = mti_CreateProcess( "SignalDriver", driveSignal, inst );
  mti_ScheduleWakeup( inst->procid, inst );
  inst->delay = 1;

  inst->i1_sigid  = mti_FindSignal( "/top/i1" );
  inst->i1_drvid  = mti_CreateDriver( inst->i1_sigid );
  mti_SetDriverOwner( inst->i1_drvid, inst->procid );

  inst->i2_sigid  = mti_FindSignal( "/top/i2" );
  inst->i2_drvid  = mti_CreateDriver( inst->i2_sigid );
  mti_SetDriverOwner( inst->i2_drvid, inst->procid );

  inst->i3_sigid  = mti_FindSignal( "/top/i3" );
  inst->i3_drvid  = mti_CreateDriver( inst->i3_sigid );
  mti_SetDriverOwner( inst->i3_drvid, inst->procid );

  inst->t1_sigid  = mti_FindSignal( "/top/t1" );
  inst->t1_drvid  = mti_CreateDriver( inst->t1_sigid );
  mti_SetDriverOwner( inst->t1_drvid, inst->procid );

  inst->t2_sigid  = mti_FindSignal( "/top/t2" );
  inst->t2_drvid  = mti_CreateDriver( inst->t2_sigid );
  mti_SetDriverOwner( inst->t2_drvid, inst->procid );

  inst->t3_sigid  = mti_FindSignal( "/top/t3" );
  inst->t3_drvid  = mti_CreateDriver( inst->t3_sigid );
  mti_SetDriverOwner( inst->t3_drvid, inst->procid );

  mti_AddLoadDoneCB( loadDoneCallback, inst );
  mti_AddQuitCB( cleanupCallback, inst );
  mti_AddRestartCB( cleanupCallback, inst );
}

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl;";
begin
end a;

library ieee;
use ieee.std_logic_1164.all;

entity top is
end top;

architecture a of top is

  signal i1 : bit := '0';
  signal i2 : std_logic := '0';
  signal i3 : bit_vector( 3 downto 0 ) := "1100";

  signal t1 : bit := '0';
  signal t2 : std_logic := '0';
  signal t3 : bit_vector( 3 downto 0 ) := "1100";

  component for_model
  end component;

begin

  forinst : for_model;

end a;

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
VSIM 1> add list /top/i1 /top/t1 /top/i2 /top/t2 /top/i3 /top/t3
VSIM 2> run 35
VSIM 3> write list list.out
VSIM 4> quit
# Cleaning up...
% cat list.out
         ns       /top/i1    /top/i3
          delta     /top/t1       /top/t3
                      /top/i2
                        /top/t2
          0  +0         0 0 0 0 1100 1100
          5  +0         0 1 0 1 1100 0011
          6  +0         0 0 0 Z 1100 1100
          8  +0         0 1 0 W 1100 0011
         11  +0         0 0 0 L 1100 1100
         15  +0         1 1 H H 0011 0011
         20  +0         0 0 - - 1100 1100
         26  +0         1 1 U U 0011 0011
         33  +0         0 0 X X 1100 1100

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