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mti_SetSignalValue()
Sets the value of a VHDL signal.
Syntax
mti_SetSignalValue( signal_id, value )Returns
Arguments
Description
mti_SetSignalValue() sets the specified VHDL signal to the specified value immediately. The signal can be either an unresolved signal or a resolved signal. Setting the signal marks it as active in the current delta. If the new value is different than the old value, then an event occurs on the signal in the current delta. If the specified signal is of type array, real, or time, then the value type is considered to be "void *" instead of "long".
mti_SetSignalValue() cannot be used to set the value of a signal of type record, but it can be used to set the values on the individual scalar or array subelements.
Setting a resolved signal is not the same as driving it. After a resolved signal is set it may be changed to a new value the next time its resolution function is executed. mti_ScheduleDriver() can be used to drive a value onto a signal.
Related functions
Example
FLI code
#include <mti.h> typedef struct signalInfoT_tag { struct signalInfoT_tag * next; char * name; mtiSignalIdT sigid; mtiTypeIdT typeid; } signalInfoT; typedef struct { signalInfoT * sig_info; /* List of signals. */ mtiProcessIdT proc; /* Test process id.*/ } instanceInfoT; static void setValue( mtiSignalIdT sigid, mtiTypeIdT sigtype ) { switch ( mti_GetTypeKind( sigtype ) ) { case MTI_TYPE_ENUM: { mtiInt32T scalar_val; scalar_val = mti_GetSignalValue( sigid ); scalar_val++; if (( scalar_val < mti_TickLow( sigtype )) || ( scalar_val > mti_TickHigh( sigtype ))) { scalar_val = mti_TickLeft( sigtype ); } mti_SetSignalValue( sigid, (long)scalar_val ); } break; case MTI_TYPE_PHYSICAL: case MTI_TYPE_SCALAR: { mtiInt32T scalar_val; scalar_val = mti_GetSignalValue( sigid ); scalar_val++; mti_SetSignalValue( sigid, (long)scalar_val ); } break; case MTI_TYPE_ARRAY: { int i; mtiTypeIdT elem_type; mtiSignalIdT * elem_list; elem_type = mti_GetArrayElementType( sigtype ); switch ( mti_GetTypeKind( elem_type ) ) { case MTI_TYPE_SCALAR: case MTI_TYPE_PHYSICAL: { mtiInt32T * array_val = mti_GetArraySignalValue( sigid, 0 ); for ( i = 0; i < mti_TickLength( sigtype ); i++ ) { array_val[i]++; } mti_SetSignalValue( sigid, (long)array_val ); mti_VsimFree( array_val ); } break; case MTI_TYPE_ARRAY: case MTI_TYPE_RECORD: default: elem_list = mti_GetSignalSubelements( sigid, 0 ); for ( i = 0; i < mti_TickLength( sigtype ); i++ ) { setValue( elem_list[i], mti_GetSignalType( elem_list[i] )); } mti_VsimFree( elem_list ); break; case MTI_TYPE_ENUM: if ( mti_TickLength( elem_type ) <= 256 ) { char * array_val = mti_GetArraySignalValue( sigid, 0 ); for ( i = 0; i < mti_TickLength( sigtype ); i++ ) { array_val[i]++; if (( array_val[i] < mti_TickLow( elem_type )) || ( array_val[i] > mti_TickHigh( elem_type ))) { array_val[i] = mti_TickLeft( elem_type ); } } mti_SetSignalValue( sigid, (long)array_val ); mti_VsimFree( array_val ); } else { mtiInt32T * array_val = mti_GetArraySignalValue( sigid, 0 ); for ( i = 0; i < mti_TickLength( sigtype ); i++ ) { array_val[i]++; if (( array_val[i] < mti_TickLow( elem_type )) || ( array_val[i] > mti_TickHigh( elem_type ))) { array_val[i] = mti_TickLeft( elem_type ); } } mti_SetSignalValue( sigid, (long)array_val ); mti_VsimFree( array_val ); } break; case MTI_TYPE_REAL: { double * array_val = mti_GetArraySignalValue( sigid, 0 ); for ( i = 0; i < mti_TickLength( sigtype ); i++ ) { array_val[i] = array_val[i] + 1.1; } mti_SetSignalValue( sigid, (long)array_val ); mti_VsimFree( array_val ); } break; case MTI_TYPE_TIME: { mtiTime64T * array_val = mti_GetArraySignalValue(sigid, 0); for ( i = 0; i < mti_TickLength( sigtype ); i++ ) { MTI_TIME64_ASGN( array_val[i], MTI_TIME64_HI32(array_val[i]), MTI_TIME64_LO32(array_val[i]) + 1 ); } mti_SetSignalValue( sigid, (long)array_val ); mti_VsimFree( array_val ); } break; } } break; case MTI_TYPE_RECORD: { int i; mtiSignalIdT * elem_list; elem_list = mti_GetSignalSubelements( sigid, 0 ); for ( i = 0; i < mti_TickLength( sigtype ); i++ ) { setValue( elem_list[i], mti_GetSignalType( elem_list[i] )); } mti_VsimFree( elem_list ); } break; case MTI_TYPE_REAL: { double real_val; mti_GetSignalValueIndirect( sigid, &real_val ); real_val += 1.1; mti_SetSignalValue( sigid, (long)(&real_val) ); } break; case MTI_TYPE_TIME: { mtiTime64T time_val; mti_GetSignalValueIndirect( sigid, &time_val ); MTI_TIME64_ASGN( time_val, MTI_TIME64_HI32(time_val), MTI_TIME64_LO32(time_val) + 1 ); mti_SetSignalValue( sigid, (long)(&time_val) ); } break; default: break; } } static void checkValues( void *inst_info ) { instanceInfoT *inst_data = (instanceInfoT *)inst_info; signalInfoT *siginfo; mti_PrintFormatted( "Time [%d,%d]:\n", mti_NowUpper(), mti_Now() ); for ( siginfo = inst_data->sig_info; siginfo; siginfo = siginfo->next ) { mti_PrintFormatted( " Signal %s = %s\n", siginfo->name, mti_SignalImage( siginfo->sigid )); setValue( siginfo->sigid, siginfo->typeid ); } mti_ScheduleWakeup( inst_data->proc, 5 ); } static signalInfoT * setupSignal( mtiSignalIdT sigid ) { signalInfoT * siginfo; siginfo = (signalInfoT *) mti_Malloc( sizeof(signalInfoT) ); siginfo->sigid = sigid; siginfo->name = mti_GetSignalNameIndirect( sigid, 0, 0 ); siginfo->typeid = mti_GetSignalType( sigid ); siginfo->next = 0; return( siginfo ); } static void initInstance( void ) { instanceInfoT * inst_data; mtiSignalIdT sigid; signalInfoT * curr_info; signalInfoT * siginfo; inst_data = mti_Malloc( sizeof(instanceInfoT) ); inst_data->sig_info = 0; for ( sigid = mti_FirstSignal( mti_GetTopRegion() ); sigid; sigid = mti_NextSignal() ) { siginfo = setupSignal( sigid ); if ( inst_data->sig_info == 0 ) { inst_data->sig_info = siginfo; } else { curr_info->next = siginfo; } curr_info = siginfo; } inst_data->proc = mti_CreateProcess( "Test Process", checkValues, (void *)inst_data ); mti_ScheduleWakeup( inst_data->proc, 5 ); } void initForeign( mtiRegionIdT region, /* The ID of the region in which this */ /* foreign architecture is instantiated. */ char *param, /* The last part of the string in the */ /* foreign attribute. */ mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/ mtiInterfaceListT *ports /* A list of ports for the foreign model. */ ) { mti_AddLoadDoneCB( initInstance, 0 ); }HDL code
entity for_model is end for_model; architecture a of for_model is attribute foreign of a : architecture is "initForeign for_model.sl;"; begin end a; library ieee; use ieee.std_logic_1164.all; entity top is type bitarray is array( 3 downto 0 ) of bit; type intarray is array( 1 to 3 ) of integer; type realarray is array( 1 to 2 ) of real; type timearray is array( -1 to 0 ) of time; type rectype is record a : bit; b : integer; c : real; d : std_logic; e : bitarray; end record; end top; architecture a of top is component for_model end component; for all : for_model use entity work.for_model(a); signal bitsig : bit := '1'; signal intsig : integer := 21; signal realsig : real := 16.35; signal timesig : time := 5 ns; signal stdlogicsig : std_logic := 'H'; signal bitarr : bitarray := "0110"; signal stdlogicarr : std_logic_vector( 1 to 4 ) := "01LH"; signal intarr : intarray := ( 10, 11, 12 ); signal realarr : realarray := ( 11.6, 101.22 ); signal timearr : timearray := ( 15 ns, 6 ns ); signal rec : rectype := ( '0', 1, 3.7, 'H', "1001" ); begin inst1 : for_model; end a;Simulation output
% vsim -c top Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl # 5.4b # vsim -c top # Loading .../modeltech/sunos5/../std.standard # Loading .../modeltech/sunos5/../ieee.std_logic_1164(body) # Loading work.top(a) # Loading work.for_model(a) # Loading ./for_model.sl VSIM 1> run 15 # Time [0,5]: # Signal bitsig = '1' # Signal intsig = 21 # Signal realsig = 16.35 # Signal timesig = 5 ns # Signal stdlogicsig = 'H' # Signal bitarr = "0110" # Signal stdlogicarr = "01LH" # Signal intarr = {10} {11} {12} # Signal realarr = {11.6} {101.22} # Signal timearr = {15 ns} {6 ns} # Signal rec = {'0'} {1} {3.7} {'H'} {"1001"} # Time [0,10]: # Signal bitsig = '0' # Signal intsig = 22 # Signal realsig = 17.45 # Signal timesig = 6 ns # Signal stdlogicsig = '-' # Signal bitarr = "1001" # Signal stdlogicarr = "1ZH-" # Signal intarr = {11} {12} {13} # Signal realarr = {12.7} {102.32} # Signal timearr = {16 ns} {7 ns} # Signal rec = {'1'} {2} {4.8} {'-'} {"0110"} # Time [0,15]: # Signal bitsig = '1' # Signal intsig = 23 # Signal realsig = 18.55 # Signal timesig = 7 ns # Signal stdlogicsig = 'U' # Signal bitarr = "0110" # Signal stdlogicarr = "ZW-U" # Signal intarr = {12} {13} {14} # Signal realarr = {13.8} {103.42} # Signal timearr = {17 ns} {8 ns} # Signal rec = {'0'} {3} {5.9} {'U'} {"1001"} VSIM 2> quit
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