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mti_FindSignal()
Syntax
signal_id = mti_FindSignal( name )Returns
Name Type Description signal_id mtiSignalIdT A handle to the VHDL signal or NULL if the signal is not foundArguments
Name Type Description name char * The name of a VHDL signalDescription
mti_FindSignal() returns a handle to the specified signal. The signal name can be either a full hierarchical name or a relative name. A relative name is relative to the current region set by the simulator's environment command. The default current region is the foreign architecture region during elaboration and the top-level region after elaboration is complete.
The name of a package signal must include the name of the package.
During elaboration, signals in design units that have not yet been instantiated will not be found by mti_FindSignal().
If the specified name is for an input port that has been collapsed due to optimizations, the handle that is returned is a handle to the actual signal connected to that port.
mti_FindSignal() cannot be used to find either subelements that are composites or multi-dimensional array subelements.
Related functions
Example
FLI code
#include "mti.h" void loadDoneCB( void * param ) { char * region_name; mtiSignalIdT sigid; mti_PrintMessage( "\nLoad Done phase:\n" ); sigid = mti_FindSignal( "s1" ); if ( sigid ) { region_name = mti_GetRegionFullName( mti_GetSignalRegion( sigid ) ); mti_PrintFormatted( "Found signal %s/%s\n", region_name, mti_GetSignalName( sigid ) ); mti_VsimFree( region_name ); } /* Signal p1 is not found here because the current context when * elaboration is complete is the top-level design unit and p1 * exists in the context /top/i1. */ sigid = mti_FindSignal( "p1" ); if ( sigid ) { region_name = mti_GetRegionFullName( mti_GetSignalRegion( sigid ) ); mti_PrintFormatted( "Found signal %s/%s\n", region_name, mti_GetSignalName( sigid ) ); mti_VsimFree( region_name ); } sigid = mti_FindSignal( "/mypkg/packsig" ); if ( sigid ) { region_name = mti_GetRegionFullName( mti_GetSignalRegion( sigid ) ); mti_PrintFormatted( "Found signal %s/%s\n", region_name, mti_GetSignalName( sigid ) ); mti_VsimFree( region_name ); } sigid = mti_FindSignal( "/top/s2" ); if ( sigid ) { region_name = mti_GetRegionFullName( mti_GetSignalRegion( sigid ) ); mti_PrintFormatted( "Found signal %s/%s\n", region_name, mti_GetSignalName( sigid ) ); mti_VsimFree( region_name ); } sigid = mti_FindSignal( "/top/s3(0)" ); if ( sigid ) { char * signal_name = mti_GetSignalNameIndirect( sigid, 0, 0 ); region_name = mti_GetRegionFullName( mti_GetSignalRegion( sigid ) ); mti_PrintFormatted( "Found signal %s/%s\n", region_name, signal_name ); mti_VsimFree( region_name ); mti_VsimFree( signal_name ); } sigid = mti_FindSignal( "toggle/a" ); if ( sigid ) { region_name = mti_GetRegionFullName( mti_GetSignalRegion( sigid ) ); mti_PrintFormatted( "Found signal %s/%s\n", region_name, mti_GetSignalName( sigid ) ); mti_VsimFree( region_name ); } } void initForeign( mtiRegionIdT region, /* The ID of the region in which this */ /* foreign architecture is instantiated. */ char *param, /* The last part of the string in the */ /* foreign attribute. */ mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/ mtiInterfaceListT *ports /* A list of ports for the foreign model. */ ) { char * region_name; mtiSignalIdT sigid; mti_AddLoadDoneCB( loadDoneCB, 0 ); mti_PrintMessage( "\nElaboration phase:\n" ); /* Signal s1 is not found here because the current context during * elaboration is the context of the foreign architecture and s1 * exists in the context /top. */ sigid = mti_FindSignal( "s1" ); if ( sigid ) { region_name = mti_GetRegionFullName( mti_GetSignalRegion( sigid ) ); mti_PrintFormatted( "Found signal %s/%s\n", region_name, mti_GetSignalName( sigid ) ); mti_VsimFree( region_name ); } sigid = mti_FindSignal( "p1" ); if ( sigid ) { region_name = mti_GetRegionFullName( mti_GetSignalRegion( sigid ) ); mti_PrintFormatted( "Found signal %s/%s\n", region_name, mti_GetSignalName( sigid ) ); mti_VsimFree( region_name ); } sigid = mti_FindSignal( "/mypkg/packsig" ); if ( sigid ) { region_name = mti_GetRegionFullName( mti_GetSignalRegion( sigid ) ); mti_PrintFormatted( "Found signal %s/%s\n", region_name, mti_GetSignalName( sigid ) ); mti_VsimFree( region_name ); } sigid = mti_FindSignal( "/top/s2" ); if ( sigid ) { region_name = mti_GetRegionFullName( mti_GetSignalRegion( sigid ) ); mti_PrintFormatted( "Found signal %s/%s\n", region_name, mti_GetSignalName( sigid ) ); mti_VsimFree( region_name ); } sigid = mti_FindSignal( "/top/s3(4)" ); if ( sigid ) { char * signal_name = mti_GetSignalNameIndirect( sigid, 0, 0 ); region_name = mti_GetRegionFullName( mti_GetSignalRegion( sigid ) ); mti_PrintFormatted( "Found signal %s/%s\n", region_name, signal_name ); mti_VsimFree( region_name ); mti_VsimFree( signal_name ); } /* Signal /top/toggle/a is not found because the toggle instance has * not yet been elaborated. */ sigid = mti_FindSignal( "/top/toggle/a" ); if ( sigid ) { region_name = mti_GetRegionFullName( mti_GetSignalRegion( sigid ) ); mti_PrintFormatted( "Found signal %s/%s\n", region_name, mti_GetSignalName( sigid ) ); mti_VsimFree( region_name ); } }HDL code
package mypkg is signal packsig : bit := '0'; end mypkg; entity for_model is port ( p1 : in bit ); end for_model; architecture a of for_model is attribute foreign of a : architecture is "initForeign for_model.sl"; begin end a; entity inv is generic ( delay : time := 5 ns ); port ( a : in bit; b : out bit ); end inv; architecture b of inv is begin b <= a after delay; end b; use work.mypkg.all; entity top is end top; architecture a of top is signal s1 : bit := '0'; signal s2 : bit := '0'; signal s3 : bit_vector( 7 downto 0 ) := "01101010"; component for_model is port ( p1 : in bit ); end component; for all : for_model use entity work.for_model(a); component inv is generic ( delay : time := 5 ns ); port ( a : in bit; b : out bit ); end component; begin i1 : for_model port map ( s1 ); s1 <= not s1 after 5 ns; s3 <= not s3 after 5 ns; packsig <= not packsig after 5 ns; toggle : inv port map ( s1, s2 ); end a;Simulation output
% vsim -c top Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl # 5.5 # vsim -c top # Loading .../modeltech/sunos5/../std.standard # Loading work.mypkg # Loading work.top(a) # Loading work.for_model(a) # Loading ./for_model.sl # # Elaboration phase: # Found signal /top/i1/p1 # Found signal /mypkg/packsig # Found signal /top/s2 # Found signal /top/s3(4) # Loading work.inv(b) # # Load Done phase: # Found signal /top/s1 # Found signal /mypkg/packsig # Found signal /top/s2 # Found signal /top/s3(0) # Found signal /top/toggle/a VSIM 1> run 10 VSIM 2> quit
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