mti_FindVar()

Finds a VHDL variable, generic, or constant by name. mti_FindVar() cannot find a shared variable that is declared in a package.

Syntax

variable_id = mti_FindVar( name ) 

Returns

Name	Type	Description
variable_id	mtiVariableIdT	A handle to the VHDL variable, generic, or constant or NULL if the object is not found

Arguments

Name	Type	Description
name	char *	The name of a VHDL variable, generic, or constant

Description

mti_FindVar() returns a handle to the specified VHDL variable, generic, or constant. The name can be either a full hierarchical name or a relative name. A relative name is relative to the current region set by the simulator's environment command. The default current region is the top-level region. For variables, the name must include the process label.

mti_FindVar() can be called successfully only after elaboration is complete.

mti_FindVar() cannot be used to find composite subelements. That is, the name cannot be a subscripted array element or a selected record field.

mti_FindVar() cannot be used to find a shared variable that is declared in a package.

Related functions

mti_FirstVar()

mti_NextVar()

Example

FLI code

#include <mti.h>

void printVarInfo( mtiVariableIdT varid )
{
  if ( varid ) {
    mti_PrintFormatted( "Found variable %s\n", mti_GetVarName( varid ) );
  }
}

void loadDoneCB( void * param )
{
  mti_PrintMessage( "\nLoad Done phase:\n" );

  printVarInfo( mti_FindVar( "/top/p1/v1" ) );
  printVarInfo( mti_FindVar( "p1/const1" ) );
  printVarInfo( mti_FindVar( "c1" ) );
  printVarInfo( mti_FindVar( "/top/sv1" ) );
  printVarInfo( mti_FindVar( "/top/toggle/proc1/count" ) );
  printVarInfo( mti_FindVar( "toggle/delay" ) );
  printVarInfo( mti_FindVar( "/top/toggle/myconst" ) );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( loadDoneCB, 0 );

  mti_PrintMessage( "\nElaboration phase:\n" );

  printVarInfo( mti_FindVar( "/top/p1/v1" ) );
  printVarInfo( mti_FindVar( "/top/p1/const1" ) );
  printVarInfo( mti_FindVar( "/top/c1" ) );
  printVarInfo( mti_FindVar( "/top/sv1" ) );
  printVarInfo( mti_FindVar( "/top/toggle/proc1/count" ) );
  printVarInfo( mti_FindVar( "/top/toggle/delay" ) );
  printVarInfo( mti_FindVar( "/top/toggle/myconst" ) );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a;

entity inv is
  generic ( delay : time := 5 ns );
  port ( a : in bit;
         b : out bit
       );
end inv;

architecture b of inv is
  constant myconst : real := 13.78;
begin
  b <= a after delay;

  proc1 : process
    variable count : integer := 0;
  begin
    count := count + 1;
    wait on a;
  end process;
end b;

entity top is
end top;

architecture a of top is

  constant c1 : integer := 42;
  shared variable sv1 : integer := 0;

  signal s1 : bit := '0';
  signal s2 : bit := '0';

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

  component inv is
    generic ( delay : time := 5 ns );
    port ( a : in bit;
           b : out bit
          );
  end component;

begin

  i1 : for_model;

  s1 <= not s1 after 5 ns;

  toggle : inv port map ( s1, s2 );

  p1 : process
    constant const1 : integer := 4;
    variable v1     : integer := 0;
  begin
    v1 := v1 + const1;
    sv1 := sv1 + 1;
    wait for 5 ns;
  end process;

  p2 : process
  begin
    sv1 := sv1 + 1;
    wait for 3 ns;
  end process;

end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
# 
# Elaboration phase:
# Loading work.inv(b)
# 
# Load Done phase:
# Found variable v1
# Found variable const1
# Found variable c1
# Found variable sv1
# Found variable count
# Found variable delay
# Found variable myconst
VSIM 1> run 10
VSIM 2> quit 

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