mti_FirstVar()

Gets the first VHDL variable, generic, or constant in a process.

Syntax

variable_id = mti_FirstVar( process_id ) 

Returns

Name	Type	Description
variable_id	mtiVariableIdT	A handle to the first VHDL variable, generic, or constant in a process or NULL if none of these items are in the process

Arguments

Name	Type	Description
process_id	mtiProcessIdT	A handle to a VHDL process

Description

mti_FirstVar() returns a handle to the first VHDL variable, generic, or constant in the specified process. mti_NextVar() can be used to get the subsequent VHDL variables, generics, and constants in the specified process.

All generics of an entity appear in every process within the associated architecture.

mti_FirstVar() resets the process used by previous calls to mti_FirstVar() and mti_NextVar(); therefore, mti_NextVar() always uses the process set by the latest call to mti_FirstVar().

Related functions

mti_FindVar()

mti_NextVar()

Example

FLI code

#include <mti.h>

void printVariables( mtiProcessIdT process, int indent )
{
  mtiVariableIdT varid;

  for ( varid = mti_FirstVar( process ); varid; varid = mti_NextVar() ) {
    if ( varid ) {
      mti_PrintFormatted( "%*cVariable %s\n", indent, ' ',
                         mti_GetVarName( varid ) );
    }
  }
}

void printProcesses( mtiRegionIdT region, int indent )
{
  mtiProcessIdT procid;

  for ( procid = mti_FirstProcess( region ); procid;
        procid = mti_NextProcess() ) {
    if ( procid ) {
      mti_PrintFormatted( "%*cProcess %s\n", indent, ' ',
                          mti_GetProcessName( procid ) );
      printVariables( procid, indent+2 );
    }
  }
}

void printHierarchy( mtiRegionIdT region, int indent )
{
  char *       region_name;
  mtiRegionIdT regid;

  region_name = mti_GetRegionFullName( region );
  mti_PrintFormatted( "%*cRegion %s\n", indent, ' ', region_name );
  indent += 2;
  printProcesses( region, indent );
  for ( regid = mti_FirstLowerRegion( region );
        regid; regid = mti_NextRegion( regid ) ) {
      printHierarchy( regid, indent );
  }
  mti_VsimFree( region_name );
}

void loadDoneCB( void * param )
{
  mti_PrintMessage( "\nLoad Done phase:\n" );
  printHierarchy( mti_GetTopRegion(), 1 );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( loadDoneCB, 0 );
  mti_PrintMessage( "\nElaboration phase:\n" );
  printHierarchy( mti_GetTopRegion(), 1 );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a;

entity inv is
  generic ( delay : time := 5 ns );
  port ( a : in bit;
         b : out bit
       );
end inv;

architecture b of inv is
begin
  b <= a after delay;

  p1 : process
    constant increment : integer := 1;
    variable count : integer := 0;
  begin
    count := count + increment;
    wait on a;
  end process;
end b;

entity mid is
  generic ( gen1 : string := "Mid" );
end mid;

architecture a of mid is

  signal s1 : bit := '0';
  signal s2 : bit := '0';
  signal s3 : bit := '0';
  signal s4 : bit := '0';

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

  component inv is
    generic ( delay : time := 5 ns );
    port ( a : in bit;
           b : out bit
         );
  end component;

begin

  testproc : process
    constant c1 : string := "mystring";
    variable v1 : bit := '0';
    variable v2 : integer := 42;
    variable v3 : real := 7.82;
  begin
    v1 := not v1;
    v2 := v2 + 2;
    v3 := v3 + 1.5;
    wait for 5 ns;
  end process;

  flip : inv port map ( s3, s4 );

  i1 : for_model;

  s1 <= not s1 after 5 ns;
  s3 <= not s3 after 5 ns;

  toggle : inv port map ( s1, s2 );

end a;

entity top is
end top;

architecture a of top is
  component mid is
    generic ( gen1 : string := "Top" );
  end component;
begin
  inst1 : mid;
end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.mid(a)
# Loading work.inv(b)
# Loading work.for_model(a)
# Loading ./for_model.sl
# 
# Elaboration phase:
#  Region /top
#   Region /top/inst1
#    Process testproc
#     Variable gen1
#     Variable c1
#     Variable v1
#     Variable v2
#     Variable v3
#    Region /top/inst1/i1
#    Region /top/inst1/flip
#     Process p1
#      Variable delay
#      Variable increment
#      Variable count
#     Process line__19
#      Variable delay
# 
# Load Done phase:
#  Region /top
#   Region /top/inst1
#    Process line__72
#     Variable gen1
#    Process line__71
#     Variable gen1
#    Process testproc
#     Variable gen1
#     Variable c1
#     Variable v1
#     Variable v2
#     Variable v3
#    Region /top/inst1/flip
#     Process p1
#      Variable delay
#      Variable increment
#      Variable count
#     Process line__19
#      Variable delay
#    Region /top/inst1/i1
#    Region /top/inst1/toggle
#     Process p1
#      Variable delay
#      Variable increment
#      Variable count
#     Process line__19
#      Variable delay
VSIM 1> run 10
VSIM 2> quit 

Model Technology Inc. Voice: (503) 641-1340 Fax: (503)526-5410 http://www.model.com sales@model.com