mti_GetRegionName()

Gets the simple name of a region.

Syntax

region_name = mti_GetRegionName( region_id ) 

Returns

Name	Type	Description
region_name	char *	The simple name of the specified region

Arguments

Name	Type	Description
region_id	mtiRegionIdT	A handle to a VHDL or Verilog region

Description

mti_GetRegionName() returns the simple name of the specified VHDL or Verilog region. The returned pointer must not be freed.

Related functions

mti_GetLibraryName()

mti_GetPrimaryName()

mti_GetRegionFullName()

mti_GetRegionSourceName()

mti_GetSecondaryName()

Example

FLI code

#include <mti.h>

void printHierarchy( mtiRegionIdT region, int indent )
{
  char *       region_name;
  mtiRegionIdT regid;

  region_name = mti_GetRegionName( region );
  mti_PrintFormatted( "%*cRegion %s\n", indent, ' ', region_name );
  indent += 2;
  for ( regid = mti_FirstLowerRegion( region );
        regid; regid = mti_NextRegion( regid ) ) {
    printHierarchy( regid, indent );
  }
}

void loadDoneCB( void * param )
{
  mti_PrintMessage( "\nLoad Done phase:\n" );
  printHierarchy( mti_GetTopRegion(), 1 );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( loadDoneCB, 0 );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a;

entity inv is
  generic ( delay : time := 5 ns );
  port ( a : in bit;
         b : out bit
       );
end inv;

architecture b of inv is
begin
  b <= a after delay;
end b;

entity mid is
end mid;

architecture a of mid is

  signal s1 : bit := '0';
  signal s2 : bit := '0';
  signal s3 : bit := '0';
  signal s4 : bit := '0';

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

  component inv is
    generic ( delay : time := 5 ns );
    port ( a : in bit;
           b : out bit
         );
end component;

begin

  flip : inv port map ( s3, s4 );

  i1 : for_model;

  s1 <= not s1 after 5 ns;
  s3 <= not s3 after 5 ns;

  toggle : inv port map ( s1, s2 );

end a;

entity top is
end top;

architecture a of top is
  component mid is
  end component;
begin
  inst1 : mid;
end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.mid(a)
# Loading work.inv(b)
# Loading work.for_model(a)
# Loading ./for_model.sl
# 
# Load Done phase:
#  Region top
#    Region inst1
#      Region flip
#      Region i1
#      Region toggle
VSIM 1> quit 

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