mti_GetRegionSourceName()

Gets the name of the source file which contains a region.

Syntax

source_name = mti_GetRegionSourceName( region_id ) 

Returns

Name	Type	Description
source_name	char *	The name of the source file which contains the specified region

Arguments

Name	Type	Description
region_id	mtiRegionIdT	A handle to a VHDL or Verilog region

Description

mti_GetRegionSourceName() returns the name of the source file which contains the specified VHDL or Verilog region. The returned pointer must not be freed.

Related functions

mti_GetLibraryName()

mti_GetPrimaryName()

mti_GetRegionFullName()

mti_GetRegionName()

mti_GetSecondaryName()

Example

FLI code

#include "mti.h"

static void printRegionInfo( mtiRegionIdT regid )
{
  char * source_name;
  char * region_name;

  if ( regid ) {
    region_name = mti_GetRegionFullName( regid );
    source_name = mti_GetRegionSourceName( regid );
    mti_PrintFormatted( "  Region %s is in File %s\n",
                       region_name, source_name );
    mti_VsimFree( region_name );
  }
}

void loadDoneCB( void * param )
{
  mti_PrintMessage( "\nLoad Done phase:\n" );
  printRegionInfo( mti_FindRegion( "top" ) );
  printRegionInfo( mti_FindRegion( "inst1" ) );
  printRegionInfo( mti_FindRegion( "inst1/i1" ) );
  printRegionInfo( mti_FindRegion( "inst1/flip" ) );
  printRegionInfo( mti_FindRegion( "inst1/toggle" ) );
}
void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  char * source_name;

  mti_AddLoadDoneCB( loadDoneCB, 0 );

  mti_PrintMessage( "\nElaboration phase:\n" );
  source_name = mti_GetRegionSourceName( region );
  mti_PrintFormatted( "  Foreign architecture region is in File %s\n",
                     source_name );
} 

HDL code

for_model.vhd 
entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a; 
inv.vhd 
entity inv is
  generic ( delay : time := 5 ns );
  port ( a : in bit;
         b : out bit
       );
end inv;

architecture b of inv is
begin
  b <= a after delay;
end b; 
mid.vhd 
entity mid is
end mid;

architecture a of mid is

  signal s1 : bit := '0';
  signal s2 : bit := '0';
  signal s3 : bit := '0';
  signal s4 : bit := '0';

  component for_model is
  end component;
  for all : for_model use entity work.for_model(a);

  component inv is
    generic ( delay : time := 5 ns );
    port ( a : in bit;
           b : out bit
         );
  end component;
  for all : inv use entity work.inv(b);

begin

  flip : inv port map ( s3, s4 );

  i1 : for_model;

  s1 <= not s1 after 5 ns;

  toggle : inv port map ( s1, s2 );

end a; 
top.vhd 
entity top is
end top;

architecture a of top is
  component mid is
  end component;
  for all : mid use entity work.mid(a);
begin
  inst1 : mid;
end a; 

Simulation output

% vcom -93 for_model.vhd inv.vhd mid.vhd top.vhd
Model Technology ModelSim SE/EE vcom 5.4b Compiler 2000.06 Jun  9 2000
-- Loading package standard
-- Compiling entity for_model
-- Compiling architecture a of for_model
-- Compiling entity inv
-- Compiling architecture b of inv
-- Compiling entity mid
-- Compiling architecture a of mid
-- Loading entity for_model
-- Loading entity inv
-- Compiling entity top
-- Compiling architecture a of top
-- Loading entity mid
% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.mid(a)
# Loading work.inv(b)
# Loading work.for_model(a)
# Loading ./for_model.sl
# 
# Elaboration phase:
#   Foreign architecture region is in File for_model.vhd
# 
# Load Done phase:
#   Region /top is in File top.vhd
#   Region /top/inst1 is in File mid.vhd
#   Region /top/inst1/i1 is in File for_model.vhd
#   Region /top/inst1/flip is in File inv.vhd
#   Region /top/inst1/toggle is in File inv.vhd
VSIM 1> quit 

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