mti_CreateRegion()

Creates a new VHDL region.

Syntax

region_id = mti_CreateRegion( parent, name ) 

Returns

Name	Type	Description
region_id	mtiRegionIdT	A handle to the new region or NULL if there is an error

Arguments

Name	Type	Description
parent	mtiRegionIdT	A handle to the parent region under which the new region is to be placed; OPTIONAL - can be NULL
name	char *	The name of the new region; OPTIONAL - can be NULL

Description

mti_CreateRegion() creates a new region with the specified name under the specified parent region. The name is converted to lower case. If the name is NULL, then the region is hidden. If the parent region is NULL, then the new region is not connected to the design hierarchy.

The new region can be created below either a VHDL region or a Verilog region. The new region is of type accForeign and of fulltype accShadow (see acc_vhdl.h).

If a region is created with no name or with no parent, the returned handle to the region must be saved as there is no way to find the region by name or by traversing the design with the region traversal functions.

Related functions

mti_FindRegion()

mti_GetTopRegion()

Example

FLI code

#include <acc_user.h>
#include <acc_vhdl.h>
#include <mti.h>

void printRegionInfo( mtiRegionIdT regid, int indent )
{
  char       * regkind;
  mtiRegionIdT subreg;

  switch ( mti_GetRegionKind( regid ) ) {
    case accArchitecture:
      regkind = "Architecture";
      break;
    case accForeign:
      regkind = "Foreign";
      break;
    case accModule:
      regkind = "Module";
      break;
    case accPackage:
       regkind = "Package";
       break;
    default:
      regkind = "Unknown";
      break;
  }
  mti_PrintFormatted( "%*cRegion %s : %s\n", indent, ' ',
                     mti_GetRegionName( regid ), regkind );
  indent += 2;
  for ( subreg = mti_FirstLowerRegion( regid ); subreg;
        subreg = mti_NextRegion( subreg ) ) {
      printRegionInfo( subreg, indent );
  }
}

void loadDone( void * param )
{
  mtiRegionIdT foreign_region = (mtiRegionIdT)param;
  mtiRegionIdT parent;
  mtiRegionIdT regid;

  (void) mti_CreateRegion( foreign_region, "reg_under_for_arch_post_elab" );

  parent = mti_HigherRegion( foreign_region );
  (void) mti_CreateRegion( parent, "region_under_parent_post_elab" );

  for (regid = mti_GetTopRegion(); regid; regid = mti_NextRegion( regid )) {
      printRegionInfo( regid, 1 );
  }
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mtiRegionIdT parent;
  (void) mti_CreateRegion( region, "region_under_foreign_arch" );

  parent = mti_HigherRegion( region );
  (void) mti_CreateRegion( parent, "region_under_parent" );

  (void) mti_CreateRegion( region, 0 );  /* Region with no name */

  mti_AddLoadDoneCB( loadDone, region );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a;

library ieee;
use ieee.std_logic_1164.all;

entity top is
end top;

architecture a of top is

  signal s1 : std_logic := '0';

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

begin
  i1 : for_model;
end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
#  Region top : Architecture
#    Region region_under_parent_post_elab : Foreign
#    Region i1 : Architecture
#      Region reg_under_for_arch_post_elab : Foreign
#      Region region_under_foreign_arch : Foreign
#    Region region_under_parent : Foreign
#  Region standard : Package
#  Region std_logic_1164 : Package
VSIM 1> run 5
VSIM 2> quit 

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