Report Window

ClockLock Section (Compilation Report)



Displays information regarding ClockLock® PLL usage (that is, altclklock megafunction usage) in the device, including parameter values you specified either by using the MegaWizard® Plug-In Manager (Tools menu) or by editing a text file. This section is omitted if the design does not include ClockLock PLLs, or if you specify a Cyclone, FLEX® 6000, MAX® 3000, MAX 7000, Stratix, or Stratix GX device for compilation.

Information is provided as follows for ACEX® 1K, APEX 20K, and FLEX 10KE devices:

Heading Description Value
Name Shows the ClockLock PLL instance name. <ClockLock PLL instance name>
Mode

Shows the value you selected for the OPERATION_MODE parameter for the altclklock megafunction.

Normal
Input Frequency Shows the input clock frequency value you specified. <frequency> MHz
Multiply Clock0 Shows the multiplication factor for the clock0 output port. <1, 2, or 4>
Output Frequency Shows the clock frequency value for the clock0 output port. This value is equal to the input frequency multiplied by the multiplication factor for the clock0 output port, and divided by the division factor for the clock0 output port. <frequency> MHz
Multiply Clock1 Shows the multiplication factor for the clock1 output port. <1, 2, or 4>
Output Frequency Shows the clock frequency value for the clock1 output port. This value is equal to the input frequency multiplied by the multiplication factor for the clock1 output port, and divided by the division factor for the clock1 output port. <frequency> MHz

 

Information is provided as follows for APEX 20KC and APEX 20KE devices:

Heading Description Value
Name Shows the ClockLock PLL instance name. <ClockLock PLL instance name>
Mode

Shows the mode you selected as the OPERATION_MODE parameter value for the altclklock megafunction.

Normal |
Zero Delay Buffer |
External Feedback |
LVDS
Input Frequency Shows the input frequency value you specified. <frequency> MHz
Phase Shift

Shows the value you specified for the OUTCLOCK_PHASE_SHIFT parameter for the altclklock megafunction. This parameter specifies the phase shift of the output clocks relative to the input clock, expressed as a time unit.

<time> <time unit>
Multiply Clock0 Shows the multiplication factor for the clock0 output port. <positive integer>
Divide Clock0 Shows the division factor for the clock0 output port. <positive integer>
Output Frequency Shows the clock frequency value for the clock0 output port. This value is equal to the input frequency multiplied by the multiplication factor for the clock0 output port, and divided by the division factor for the clock0 output port. <frequency> MHz
Multiply Clock1 Shows the multiplication factor for the clock1 output port. <positive integer>
Divide Clock1 Shows the division factor for the clock1 output port. <positive integer>
Output Frequency Shows the clock frequency value for the clock1 output port. This value is equal to the input frequency multiplied by the multiplication factor for the clock1 output port, and divided by the division factor for the clock1 output port. <frequency> MHz

 

Information is provided as follows for Mercury devices:

Heading Description Value
Name Shows the ClockLock PLL instance name. <ClockLock PLL instance name>
Mode

Shows the mode you selected as the OPERATION_MODE parameter value for the altclklock megafunction.

Normal |
Zero Delay Buffer |
External Feedback
Input Frequency Shows the input clock frequency value you specified. <frequency> MHz
Phase Shift

Shows the value you specified for the OUTCLOCK_PHASE_SHIFT parameter for the altclklock megafunction. This parameter specifies the phase shift of the output clocks relative to the input clock, expressed as a time unit.

<time> <time unit>
Multiply Clock0 Shows the multiplication factor for the clock0 output port. <positive>
Divide Clock0 Shows the division factor for the clock0 output port. <positive integer>
Delay Clock0 Shows the time delay value you specified for the clock0 output port. <time> <time unit>
Output Frequency Shows the clock frequency value for the clock0 output port. This value is equal to the input frequency multiplied by the multiplication factor for the clock0 output port, and divided by the division factor for the clock0 output port. <frequency> MHz
Multiply Clock1 Shows the multiplication factor for the clock1 output port. <positive integer>
Divide Clock1 Shows the division factor for the clock1 output port. <positive integer>
Delay Clock1 Shows the time delay value you specified for the clock1 output port. <time> <time unit>
Output Frequency Shows the clock frequency value for the clock1 output port. This value is equal to the input frequency multiplied by the multiplication factor for the clock1 output port, and divided by the division factor for the clock1 output port. <frequency> MHz
Multiply Clock2

Shows the multiplication factor for the clock2 output port.

<positive integer>
Divide Clock2

Shows the division factor for the clock2 output port.

<positive integer>
Delay Clock2

Shows the time delay value you specified for the clock2 output port.

<time> <time unit>
Output Frequency

Shows the clock frequency value for the clock2 output port. This value is equal to the input frequency multiplied by the multiplication factor for the output port, and divided by the division factor for the output port.

<frequency> MHz
Multiply Ext. Clock

Shows the multiplication factor for the clock_ext output port.

<positive integer>
Divide Ext. Clock

Shows the division factor for the clock_ext output port.

<positive integer>
Delay Ext. Clock

Shows the time delay value you specified for the clock_ext output port.

<time> <time unit>
Output Frequency

Shows the clock frequency value for the clock_ext output port. This value is equal to the input frequency multiplied by the multiplication factor for the output port, and divided by the division factor for the output port.

<frequency> MHz

 

The following example shows a portion of the ClockLock section generated for a sample design:


ClockLock Section (Compilation Report)


ClockLock Section (Compilation Report)

Back to Top

- PLDWorld -

 

Created by chm2web html help conversion utility.