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Lists information about the registers created or deleted during retiming for the design. This section is omitted if you did not turn on Perform gate-level register retiming, in the Netlist Optimizations page in the Settings dialog box (Assignments menu), if the design did not have any registers created or deleted during retiming, or if you did not select a APEX™ 20K, APEX™ II, ARM®-based Excalibur™, Cyclone™, Stratix™, or Stratix™ GX device for compilation.
Information is provided as follows:
| Heading | Description | Value |
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| Register Name | Shows the name of the register created or deleted during retiming. | <register name> |
| Clock Name | Shows the clock name for the domain from which the register was created or deleted. | <clock name> |
| Created/Deleted | Shows whether the register was created or deleted during retiming. | Created | Deleted |
The following example shows a portion of the Gate-level Retiming section generated for a sample design:
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- PLDWorld - |
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