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Displays the minimized equations for all logic in the project.
The equations, which represent the results of extensive logic synthesis, are provided as reference information. Because logic synthesis minimizes the logic required to implement a design, redundant or unnecessary logic in the original design files may not appear in this Report section.
A node name in the equation can have any one of the following formats:
| Format Note (1) | Description | Example |
|---|---|---|
| <Name> | Used for the input and output pins of the current design entity. This format is also used on buried node names in the compilation focus when the same buried node name remains following compilation. Synthesized names, however, are not used. | updown |
| <Entity><Instance>_<Name> | Used for nodes in hierarchy levels below the current design entity where you have assigned names to the nodes. The hierarchy level is represented by <Entity><Instance>. | B1_carrybit[3] |
| <Entity><Instance><Type><Index> [Q] | Used for nodes that are created or synthesized during compilation. | B1L7Q or C3M5 |
| <Any One of the Above Formats>_EQ[<nn>] | Used for nodes to which you assigned a temporary name. The name is formed by adding the suffix, _EQ[<nn>], to one of the other formats. | B1_carrybit[8]_EQ4 |
Equations include the following components:
| Component | Description |
|---|---|
CASCADE |
Represents a CASCADE buffer inserted by the Logic Synthesizer. |
CARRY |
Represents the CARRY output of a CARRY_SUM buffer. |
SUM |
Represents the SUM output of a CARRY_SUM buffer. |
DFFE |
Represents a <Q output> = The ports listed in this section may differ from those listed in the Help topic for the |
DFFEA |
Represents a <Q output> = The ports listed in this section may differ from those listed in the Help topic for the |
GXB_RX |
Represents GXB receiver channel usage in Stratix™ GX devices. <node> = GXB_RX.<output port>
(.DATAIN(<node>),
(.XGMDATAIN(<node>),
(.MASTERCLK(<node>),
(.CORECLK(<node>),
(.CRUCLK(<node>),
(.PLLCLK(<node>),
(.SOFTRESET(<node>),
(.SERIALFBK(<node>),
(.SLPBK(<node>),
(.BITSLIP(<node>),
(.ENACDETECT(<node>),
(.WRITEENABLE(<node>),
(.READENABLE(<node>),
(.ALIGNSTATUS(<node>),
(.DISABLEFIFORDIN(<node>),
(.DISABLEFIFOWRIN(<node>),
(.FIFORDIN(<node>),
(.ENABLEDESKEW(<node>),
(.FIFORESETRD(<node>),
(.XGMCTRLIN(<node>),
(.PARALLELFBK(<node>),
(.POST8B10B(<node>). |
GXB_TX |
Represents GXB transmitter channel usage in Stratix GX devices. <node> = GXB_TX.<output port>
(.DATAIN(<node>),
(.SERIALDATAIN(<node>),
(.XGMDATAIN(<node>),
(.CORECLK(<node>),
(.PLLCLK(<node>),
(.FASTPLLCLK(<node>),
(.SOFTRESET(<node>),
(.XGMCTRL(<node>),
(.SLPBK(<node>),
(.CTRLENABLE(<node>),
(.FORCEDISPARITY(<node>). |
XGMII |
Represents XGMII state machine usage in Stratix GX devices. <node> = XGMII.<output port>
(.TXDATAIN(<node>),
(.RXDATAIN(<node>),
(.TXCLK(<node>),
(.RXCLK(<node>),
(.RECOVCLK(<node>),
(.TXCTRL(<node>),
(.RXCTRL(<node>),
(.RDENASYNC(<node>),
(.RESETALL(<node>),
(.ADET(<node>),
(.SYNCSTATUS(<node>),
(.RDALIGN(<node>),
(.RXRUNNINGDISP(<node>),
(.RXDATAVALID(<node>). |
HSDI_PLL |
Represents HSDI PLL usage in Mercury™ devices.HSDI_PLL = (<clock,>, <reset>). |
HSDI_PLL |
Represents HSDI PLL usage in Mercury devices.HSDI_PLL = (<clock,>, <reset>). |
HSDI_RX |
Represents HSDI receiver usage in Mercury devices.HSDI_RX = (<clock,>, <data in>, <feedback>, <feedback control>, <areset>). |
HSDI_TX |
Represents HSDI transmitter usage in Mercury devices.HSDI_TX = (<clock,>, <data in>, <feedback>, <feedback control>, <areset>). |
LVDS_RX |
Represents LVDS receiver usage in APEX™ 20KE, APEX™ II, and ARM®-based Excalibur™ devices.LVDS_RX = (<>, <dskew>, <clock1>, <clock0>, <data in>). |
LVDS_TX |
Represents LVDS transmitter usage in APEX 20KE, APEX II, and ARM-based Excalibur devices.LVDS_RX = (<clock1>, <clock0>, <data in> |
MEMORY |
Represents memory in Stratix™ and Stratix GX devices. <data output> = MEMORY (<port A data input>, <port B data input>, <port A address>, <port B address>, <port A write enable>, <port B read/write enable>, <port A byte mask>, <port B byte mask>, <clock0>, <clock1>, <clock enable0>, <clock enable1>, <clear0>, <clear1). |
MEMORY_SEGMENT |
Represents memory in all device supported by the Quartus® II software except Stratix and Stratix GX devices. <data output> = MEMORY_SEGMENT (<clock0>, <clock1>, <clock enable0>, <clock enable1>, <write enable0>, <read enable>, <clear0>, <clear1> <data input>, <write address>, <read address>). |
PLL |
Represents ClockLock® PLL usage in ACEX® 1K, APEX 20K, and FLEX 10KE devices.PLL = (<clock>). |
PLL |
Represents ClockLock PLL usage in APEX 20KE, ARM-based Excalibur, and Mercury devices.PLL = (<clock>, <feedback>, <clock enable>). |
PLL |
Represents fast and enhanced PLL usage in Stratix and Stratix GX devices. <node> = PLL.<output port> (.FBIN(<node>), .ENA(<node>), .CLKSWITCH(<node>), .ARESET(<node>), .PFDENA(<node>), .SCANCLK(<node>), .SCANACLR(<node>), .SCANDATA(<node>), .COMPARATOR(<node>), .INCLK(<node>), .INCLK(<node>), .CLKENA(<node>), .CLKENA(<node>), .CLKENA(<node>), .CLKENA(<node>), .CLKENA(<node>), .CLKENA(<node>), .EXTCLKENA(<node>), .EXTCLKENA(<node>), .EXTCLKENA(<node>), .EXTCLKENA(<node>)). |
SERDES_RX |
Represents a SERDES receiver. <node> = SERDES_RX.<data output>(.DATAIN(<node>), .CLK0(<node>), .ENABLE0(<node>), .ENABLE1(<node>)). |
SERDES_TX |
Represents a SERDES transmitter. <node> = SERDES_RX.<data output>(.DATAIN(<node>), .CLK0(<node>), <data input>). |
INPUT |
Represents the input pin. <pin name> = INPUT (). |
OUTPUT |
Represents the output pin. <pin name> = OUTPUT (<node>). |
BIDIR |
Represents the bidirectional pin. <pin name> = BIDIR (<node>). |
TRI_BUS |
Represents a tri-state bus that is made up of multiple inputs, any one of which drives a net output. |
TRI |
Represents a tri-state node. <pin name> = TRI (<input>, <output enable>). |
GLOBAL |
Represents a global signal driven by a dedicated input pin or internal logic. <pin name> = GLOBAL (<node>). |
MUX |
Represents a 2:1 MUX.<Q output> = MUX (<data0>, <data1>, <select>, <enable>). |
CARRY_SUM |
Represents a CARRY_SUM buffer. |
LATCH |
Represents a latch. <Q output> = LATCH (<D input>, <latch enable>). |
& |
AND operator. |
$ |
XOR (exclusive OR) operator. |
# |
OR operator. |
! |
NOT operator. |
Each equation or set of equations is preceded by comments describing the node name, the node source if from a text-based design file, and node location. For example:
--B1_carrybit[8] is |LPM_COUNTER:inst1|carrybit[8] at LC8_1_A1
The following example shows a portion of the Equations section for a sample design:
Legend:
| Single-line comments | Green |
| Keywords | Blue |
| Reserved identifiers (AHDL) | Dark Purple |
| Synthesized logic cells | Names that include ~ characters |
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This topic prints best in Landscape orientation. |
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