See Also

For ACEX® 1K, FLEX 10KE, and Mercury™ devices, all flipflops are reported as DFFEA primitives.

FUNCTION DFFEA (D, CLK, CLRN, PRN, ENA, ADATA, ALOAD)
   RETURNS (Q);

COMPONENT DFFEA
   PORT (d   : IN STD_LOGIC;
      clk 	: IN STD_LOGIC;
      clrn	: IN STD_LOGIC;
      prn 	: IN STD_LOGIC;
      ena 	: IN STD_LOGIC;
      adata	: IN STD_LOGIC;
      aload	: IN STD_LOGIC;	  	  
      q   	: OUT STD_LOGIC );
END COMPONENT;

Inputs CLRN PRN ALOAD ADATA ENA D CLK	Output Q
L H L X X X X H L L X X X X L L L X X X X H H L X L X X H H L X H L H H L X H H H H L X X X L H H H H X X X H H H L X X X L H H X X X X H L H X X X X	L H Illegal Qo* L H Qo* H L Illegal Illegal

* Qo = level of Q before clock pulse

All flipflops are positive-edge-triggered.

When the ENA (clock enable) input is high, the flipflop passes a signal from D to Q. When the ENA input is low, the state of Q is maintained, regardless of the D input.

For devices that do not support clock enable, logic synthesis generates logic equations representing flipflops with clock enables. These logic equations correctly emulate the logic specified in the project.

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