csfifo (Cycle-Shared FIFO) Megafunction

Parameterized cycle-shared FIFO megafunction. Altera^® recommends that you use lpm_fifo instead of csfifo for single-clock FIFO functions, and that you use lpm_fifo_dc instead of csfifo for dual-clock FIFO functions. The csfifo function uses Embedded System Blocks (ESB) in APEX^™ 20K, APEX^™ II, ARM^®-based Excalibur^™, and Mercury^™ devices, Embedded Array Blocks (EAB) in ACEX^® 1K and FLEX 10KE devices, or DFFE primitives or latch arrays in FLEX^® 6000, MAX^® 3000, and MAX 7000 devices or if the USE_EAB parameter is set to "OFF". Altera strongly recommends using synchronous rather than asynchronous RAM functions. The csfifo megafunction is is provided only for backward compatibility only, and is not available for Cyclone^™, Stratix^™, and Stratix^™ GX designs.

The Quartus^® II Compiler automatically implements suitable portions of this function in ESBs in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, and in EABs in ACEX 1K and FLEX 10KE devices. The Compiler automatically implements this function in logic cells in FLEX 6000, MAX 3000, and MAX 7000 devices devices.

This topic contains the following information:

AHDL Function Prototype (also applies to Verilog HDL)
VHDL Component Declaration
VHDL LIBRARY-USE Declaration (not required if the VHDL Component Declaration is used)
Port Descriptions
Parameter Descriptions

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION csfifo (data[(LPM_WIDTH)-(1)..0], wreq, rreq, clock,
      clockx2, clr, threshlevel[CEIL(LOG2(LPM_NUMWORDS))-1..0])
   WITH (LPM_WIDTH, LPM_NUMWORDS)
   RETURNS (q[(LPM_WIDTH)-(1)..0], threshold, empty, full,
      usedw[CEIL(LOG2(LPM_NUMWORDS))-1..0]);

VHDL Component Declaration:

COMPONENT csfifo
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_NUMWORDS: POSITIVE);
   PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      wreq, rreq, clock, clockx2, clr: IN STD_LOGIC;
      empty, full: OUT STD_LOGIC;
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

The VHDL Component Declaration for the csfifo megafunction does not include the threshlevel[], threshold, or usedw[] ports because these signals are not supported in Quartus II VHDL.

VHDL LIBRARY-USE Declaration

LIBRARY lpm;
USE lpm.lpm_components.all;

Port Descriptions:

INPUT PORTS

Port Name	Required	Description	Comments
`data[]`	Yes	Data input to the `csfifo`.	Input port `LPM_WIDTH` wide.
`wreq`	Yes	Write request.
`rreq`	Yes	Read request.
`clock`	Yes	Positive-edge-triggered clock.
`clockx2`	Yes	Positive-edge-triggered clock operating at twice the frequency of `clock`.
`clr`	No	Resets `csfifo` to empty.
`threshlevel[]`	No	Level (number of words) that the threshold output signal asserts.	Input port with width `[CEIL(LOG2(LPM_NUMWORDS))-1..0]`.

OUTPUT PORTS

Port Name	Required	Description	Comments
`q[]`	Yes	Data output from `csfifo`.	Output port `LPM_WIDTH` wide.
`full`	No	Indicates that `csfifo` is full.
`empty`	No	Indicates that `csfifo` is empty.
`threshold`	No	Indicates that `csfifo` contains greater than the `threshlevel[]` number of words.
`usedw`	No	The number of `csfifo` words that are currently being used. If the value of `LPM_NUMWORDS` is a power of 2, you can use the `full` output as an extra bit and append it to `usedw[]`. Example The `csfifo` must contain at least one word before it is able to read the word and must have at least one unused word before it is able to write a word.	Output port with width `[CEIL(LOG2(LPM_NUMWORDS))-1..0]`.

Parameter Descriptions:

Parameter Type Required Description

LPM_WIDTH Integer Yes Width of data[] and q[] ports.

LPM_NUMWORDS Integer Yes Number of words stored in memory, which is usually a power of 2.

Parameter	Type	Required	Description
`LPM_WIDTH`	Integer	Yes	Width of `data[]` and `q[]` ports.
`LPM_NUMWORDS`	Integer	Yes	Number of words stored in memory, which is usually a power of 2.
`USE_EAB`	String	No	Altera-specific parameter. Values are `"ON"`, `"OFF"`, and `"UNUSED"`. Setting the `USE_EAB` parameter to `OFF` prevents the Quartus II software from using ESBs to implement the logic in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, or EABs in ACEX 1K and FLEX 10KE devices; it can only use flipflops or latches. (The `"ON"` setting is not useful in memory functions: the Quartus II software automatically implements memory functions in ESBs or EABs by default.) This parameter is not available for simulation with other EDA simulators and for FLEX 6000, MAX 3000, and MAX 7000 devices. If you wish to use this parameter when you instantiate the function in a Block Design File (.bdf), you must specify it by entering the parameter name and value manually with the Parameters tab (Symbol Properties Command) or the Parameters tab (Block Properties Command). You can also use this parameter name in a Text Design File (.tdf) or a Verilog Design File (.v). You must use the `LPM_HINT` parameter to specify the `USE_EAB` parameter in VHDL Design Files (.vhd).

USE_EAB

String

Altera-specific parameter. Values are "ON", "OFF", and "UNUSED". Setting the USE_EAB parameter to OFF prevents the Quartus II software from using ESBs to implement the logic in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, or EABs in ACEX 1K and FLEX 10KE devices; it can only use flipflops or latches. (The "ON" setting is not useful in memory functions: the Quartus II software automatically implements memory functions in ESBs or EABs by default.) This parameter is not available for simulation with other EDA simulators and for FLEX 6000, MAX 3000, and MAX 7000 devices.

If you wish to use this parameter when you instantiate the function in a Block Design File (.bdf), you must specify it by entering the parameter name and value manually with the Parameters tab (Symbol Properties Command) or the Parameters tab (Block Properties Command). You can also use this parameter name in a Text Design File (.tdf) or a Verilog Design File (.v). You must use the LPM_HINT parameter to specify the USE_EAB parameter in VHDL Design Files (.vhd).

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