The worst-case requirement that should be met to ensure that the correct data is stable long enough on a destination register for the register to latch the data. The Timing Analyzer uses the most restrictive hold relationship when analyzing paths between registers that are clocked by different clocks. The Timing Analyzer performs the following two hold checks to verify that each design meets the conditions of the default hold relationship:
| Hold relationship check 1 | Verifies that data from the source clock edge, which follows the setup launch edge, is not latched by the setup latch edge. |
| Hold relationship check 2 | Verifies that data from the setup launch edge is not latched by the destination clock edge that precedes the setup latch edge. |
The following illustration shows the default multifrequency setup and hold relationships for a path from a clk1 register and a clk2 register:
You can directly override this default hold relationship in various ways by assigning any of the following timing assignments:
The following illustration shows how assigning a Multicycle Hold value of 2 affects the hold relationship:
Assigning a Multicycle, Source Multicycle, Enable Multicycle, and/or Enable Source Multicycle assignment indirectly affects the hold relationship by delaying the latch edge of a clocked register. For example, the following illustration shows the multifrequency setup and hold relationships for a path between a clk1 register and a clk2 register when Multicycle equals 2 and Hold Multicycle equals 1:
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