Allows you to change the hold relationship of all enable-driven registers of the assigned pin or register by specifying the minimum number of clock cycles required before an enable-driven register latches a value. In other words, the Enable Multicycle Hold assignment allows you to assign a Multicycle Hold value to all enable-driven registers directly fed by the assigned register or pin.

For example, if you assign a Enable Multicycle Hold requirement of 2 to a clocked register, the signal must travel from the source to the destination register in no less than two clock cycles in order to meet the requirement. This requirement affects every enable-driven register of the assigned register or pin, as shown in the following illustration:

Similarly, assigning a point-to-point Enable Multicycle Hold affects all register to register paths in which the source and destination registers directly feed an enable-driven register, as shown in the following illustration:

The following table prioritizes each legal assignment type, and shows which paths are affected when assigned. Priority 1 assignments take precedence over priority 2 assignments, and so on. Within a priority level, the most stringent requirement takes precedence. Specifying a point-to-point Enable Multicycle Hold assignment may increase the time necessary for timing-driven compilation.