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After you compile a project, you can use the Floorplan Editor to view the Compiler's logic placement. You can then compare the project's assignments to the Compiler's assignments, if they differ, and back-annotate the results of compilation.
In the Floorplan Editor, you can select device resources and view the routing information for selected items:
You can display paths between nodes.
You can display node fan-in and fan-out for selected nodes.
You can display routing delays for connections shown.
You can display connection counts for connections shown.
You can display routing statistics for selected items.
You can display a physical timing estimate for a selected LAB in the Timing Closure floorplan.
You can display critical paths in the design.
You can display path edges for a selected critical path.
You can display routing congestion in the design.
You can display LogicLock™ regions.
You can display LogicLock region connectivity for connected LogicLock regions.
You can display intra-region delay in LogicLock regions.
You can maintain connections to and from assignments as you move them by turning on rubberbanding.
You can choose to display only user assignments, to display only fitter placements, or to display both types of assignments in the Timing Closure floorplan.
You can show resource usage for each LAB or MegaLAB™ structure in the form of numbers and histograms.
You can also change the colors for the lines and labels displaying routing information.
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