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To show or hide the paths between individual logic cells along a critical path in a design in the Floorplan Editor:

1. Open the Current Assignments floorplan, open the Last Compilation floorplan, or open the Timing Closure floorplan.

2. Specify critical path settings.

3. Turn on Routing > Show Routing Delays (View menu). Shortcut.

4. To show the paths between individual logic cells along a critical path, right-click the routing delay on a critical path and choose Show Path Edges (right button pop-up menu).

5. To hide the paths between individual logic cells along a critical path, right-click the routing delay on a critical path and choose Hide Path Edges (right button pop-up menu).

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