Overviews

Commands

See Also

To show the maximum time delay between source and destination paths in a LogicLock^™ region, including its child regions in the Floorplan Editor:

1. If you have not already done so, create a LogicLock region.

2. If you have not already done so, compile the design.

3. Open the Last Compilation floorplan, or open the Timing Closure floorplan.

4. Choose Routing > Show Intra-region Delay (View menu).  Shortcut

5. Place the pointer over the desired LogicLock region to view the intra-region delay in the tooltip.

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