Overviews

Commands

See Also

To use the Model Technology ModelSim PE or SE (non-OEM) software to perform a functional simulation of a VHDL or Verilog HDL design that contains Altera-specific components:

1. If you have not already done so, perform 2. Set Up a Project with the ModelSim Software.

2. To map the design libraries to your work library:

   1. Choose New > Library (File menu). The Create a New Library dialog box appears.

   2. Type lpm in the Library Name box, type the name of the work library in the Library Maps to box, and click OK.

   3. Repeat steps 2a and 2b to map altera_mf to the work library.

3. If your design contains the altgxb megafunction, to map to the precompiled Stratix GX functional simulation model libraries:

   1. Choose New > Library (File menu). The Create a New Library dialog box appears.

   2. Under Create, select a new library and a logical mapping to it.

   3. In the Library Name box, type altgxb.

   4. In the Library Maps to box, specify the \quartus\eda\sim_lib\modelsim\<verilog or vhdl>\altgxb\ directory.

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

4. If your Verilog HDL design contains content-addressable memory (CAM), RAM, or ROM functions, and you are using a Hexadecimal (Intel-Format) File (.hex), you can convert them for use with the ModelSim software using the convert_hex2ver utility.

The ModelSim software does not support using Memory Initialization Files (.mif) to specify the initial content of memory in CAM, RAM, and ROM functions using the convert_hex2ver utility.

5. If your Verilog HDL design contains CAM, RAM, or ROM functions, and you are using a HEX or MIF File, to convert memory initialization file for use with the ModelSim software without using the convert_hex2ver utility:

   1. Export the HEX or MIF File as a RAM Initialization File (.rif) in the Quartus II software.

   2. Add parameter lpm_file = "<RIF name>.rif"; for the CAM, RAM, or ROM function to your top-level design or test bench file.

   3. Select Compile (Design menu).

   4. In the Compile HDL Source Files dialog box, click Default Options.

   5. In the Compiler Options dialog box, click the Verilog tab.

   6. Click Macro. In the Define Macro box, type NO_PLI.

   7. Click OK.

   8. Click Apply.

6. To compile the functional simulation libraries, Verilog or VHDL Design Files, and test bench files (if you are using a test bench):

   1. Choose Compile (Compile menu).

   2. In the Library list of the Compile HDL Source Files dialog box, select the work library.

   3. In the File name list, type the directory path and file name of the functional simulation libraries.

      or

      In the Files of Type list, select All Files (*.*), and in the Look in list select the Verilog or VHDL Design File.

   4. Click Compile.

   For VHDL designs that use the 220model.vhd library, turn on Use Explicit Declarations under Default Options in the Compile dialog box. For VHDL 93-compliant designs, turn on Use 1993 Language Syntax under Default Options.

   5. If you are performing a functional simulation of an ARM-based Excalibur design, repeat steps 6b to 6d to compile the appropriate ARM-based Excalibur simulation model wrapper file.

   6. Repeat steps 6b to 6d to compile the Verilog or VHDL Design File.

   7. Repeat steps 6b to 6d to compile the test bench file(s).

   8. Click Done.

7. To load the design:

   1. Choose Simulate (Simulate menu). The Simulate dialog box appears.

   2. In the Name list, click the + icon to expand the work directory.

   3. Select the top-level design file to simulate.

   4. Click Add.

   5. Click Load.

8. Perform the functional simulation in the ModelSim software.

If you are simulating an ARM-based Excalibur design, the bus functional model generates the output.dat bus functional model simulation file. Refer to ModelSim software documentation for more information on how to view and interpret the results of the simulation.

9. To continue with the ModelSim simulation flow, return to one of the following steps:

   • 2. Set Up a Project with the ModelSim Software
   • 2. Set Up a Project with the ModelSim Software (Command-Line)

Back to Top