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After you set up the project, you can perform a functional simulation of an ARM^®-based Excalibur^™ Verilog or VHDL design with an instantiation of alt_exc_stripe using the Excalibur Stripe Simulator (ESS) model with the Model Technology^™ ModelSim^® software.

You can use the ESS model to simulate Verilog designs with the ModelSim PE/SE (non-OEM) and ModelSim-Altera® (OEM) software, and simulate VHDL designs with the ModelSim SE software.

To load the design and run the simulation:

1. If you have not already done so, perform 1. Set Up the Project with the ModelSim Software for Use with the ESS Model.

2. To load the design:

   1. Choose Simulate (Simulate menu). The Simulate dialog box appears.

   2. In the Name list, click the + icon to expand the work directory.

   3. Select the top-level design file or test bench file to simulate.

   4. Click Add.

   5. Click Load.

3. To perform the functional simulation in the ModelSim software, choose Run > Run -All (Simulate menu).

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