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Specifies the following timing requirements, which the Quartus® II software includes in the HardCopy™ files it generates, or which you need to estimate power requirements for a design you are converting for HardCopy devices:
| Minimum required Tco | The minimum acceptable tCO (clock-to-output delay) for the entire project. |
| Minimum required Tpd | The minimum acceptable tPD (pin-to-pin delay) for the entire project. |
| Default external clock jitter | The maximum acceptable external clock jitter for the entire project. |
These project-wide timing requirements are not available for other Quartus II designs, but are necessary for generating HardCopy files or estimating the power consumption of HardCopy designs.
The Quartus II software uses these timing requirements when generating HardCopy files during or after a compilation, and only for designs that target one of the following APEX™ 20KC, APEX 20KE, or APEX™ II devices:
The HardCopy HC20K Power Calculator page in the Altera® web site, which you can use to estimate power consumption, uses these timing requirements only for designs that target one of the following APEX 20KC or APEX 20KE devices:
You can also specify minimum required tCO and minimum required tPD timing requirements for individual pins using the By Node tab of the Assignment Organizer dialog box (Assignment menu).
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