EE 4743/6743 Digital System Design (Spring 2003)

Policy/Syllabus

Policy/Syllabus

Teaching Philosophy

This is an upper level course, and thus is taught in a different style than what I use in a lower level course. READ THIS -- it will give you a clue as to what to expect in this class.

Email List

The class EMAIL list will be the one provided by Information Technology Services (ITS). The email list is ece4743-01.spring2003@courses.msstate.edu . All students will be on this list, regardless of what section you are registered for. See the Class EMAIL Faq for further information about class email lists.

WARNING!!! It is your responsibility to make sure that you are able to read email sent to this list (the list uses your official MSU email address). I will send many homework/test/lecture announcements to this list -- you are responsible for reading the emails sent to this list.

ECE HelpDesk

Please visit the ECE HelpDesk Site for general questions about ECE computing facilities. If you are a new student and have registered well in advance you will have an account on ECE machines. New stduents may pick up their accounts slips (has username, password) from the main office. Students who registered close to the start of classes accounts during the first week of class.

Maxplus Software

We will be using a software package called 'Altera Maxplus' for digital logic simulation in this class. Your textbook has a CDROM of this software package on the back cover. We will discuss how to install and use the software in class. Your book also has a good tutorial on the software in Appendix B. This same software is available on the Unix workstations in the ECE department.

Download the Student Edition Software (v. 10.2) Directly from Altera Website HERE.

Obtain a license file from Altera for either version 10.1 or version 9.23 from HERE .

Spring 2003 Lab Instructors, Lab Policy

Anitha Govindarajan ag128@ece.msstate.edu

"Ram" Ramakrishnan Nagakrishnan, Phone: 325-9476 rn1@ece.msstate.edu

This Lab Policy Document will be used for the Spring 2003 semester.

WebCT Course Ware

I will be using a University WWW resource called 'WebCT' for some homework assignments. To access the ECE 4743 WebCT course page, go to the WebCT home page , and click on the "Log into myWebCT" option. You will need to use your MSU NetID and password to login into WebCT. If you do not know your MSU Netid, look it up in the online campus directory: http://www.msstate.edu/directory , the MSU NetID is right next to your name. If you have never logged into a WebCT course before, the login name is your MSU NetID, the default passwd is your 6-digit birthdate (mmddyy). Once you have logged into WebCT, use the Password Tool ("Change Password" in upper right corner) to change your password.

Once you are logged into WebCT, you should see under "Courses" on the left-hand side the course "ECE 4743-Digital System Design" (if you do not see this then this means that you have not been added yet - please send me email at reese@ece.msstate.edu and I will add you to the course). Click on the course name to access the course. I will be using WebCT only for online homework quizzes. To take a WebCT quiz, click on the Online Quizzes once you have accessed the course . You will be presented with a list of multiple choice questions. After choosing an answer for a question, click on the 'submit answer' button. This MUST BE DONE FOR EACH QUESTION. Simply choosing an answer does not submit the answer, you must click on the "submit answer" button. There is a chart on the right side that will show how many questions have answers submitted for them; don't leave the quiz until you have answered all of the questions.

Some of the questions will be in short answer format instead of multiple choice - it is important that you follow the question directions in terms of answer format because answer checking is done via string matching, and if you don't use the correct format for your answer it will be graded as wrong even though your answer is technically correct.

Homework Assignments

I have enabled quizzes 8, 9 and 10 in the ECE 4743 WebCT course -- these are quizzes that review basic Digital Devices concepts. The cutoff date for completing these quizzes is January 22nd. I will not count these quiz results in a formal way in the grade average, but will use them for making decisions for bordeline students when I assign final grades at the end of the semester. Taking these quizzes should help you in understanding the review material. The review material does not cover all of the quiz topics - you can find additional information on these topics at my home page for Digital Devices . When taking a quiz, you will be presented with all of the questions at once. After answering the questions, press the 'submit' button, and you will be shown which questions were correct or incorrect (for incorrect answers, the correct answer is NOT shown). You can take the quiz twice - the highest of the two grades will be the grade that I will use for borderline decisions.

Test Seating Spring 2003

Here is the Seating Chart that will be used for all tests.

Spring 2003 Labs

See the lab policy document for lab report requirements. While the lab reports are very informal in this class, lab reports are required. A lab report is NOT REQUIRED for Lab #0. Lab reports are required for Labs 1 through 5. Lab reports are required for all three parts of Lab #6. A lab report is required only for the 2nd portion of Lab #7. A lab report required for Lab #8.

Lab 0 (HTML): Maxplus Tutorial (first week of class)
Lab 1 (PDF, updated Spring 2003)
Lab 2 Signed/Unsigned Saturating Adder, Updated Spring '02 , lab2.zip - contains files needed for assignment , Lab 2 Post-lab Questions
Lab 3 (HTML): Intro to Altera LPMs, Datapaths , Lab 3 Post-lab Questions
Lab 4: Timing, Pipelining , files.zip - contains files needed for assignment , Post-Lab questions (answer these in your lab report)
Lab 5: A FSM + Datapath Problem - Block Transfer Ram , files.zip - contains files needed for assignment
Lab 6, Part #1: Bilinear Filtering Lab assignment , PDF file , bifilt_students.zip - Files needed for this assignment
Lab 6, Part #2: Bilinear Filtering Lab assignment , PDF file , tb_bifiltp2_gold.zip - Files needed for this assignment
Lab 6, Part #3: Bilinear Filtering Lab assignment , PDF file , tb_bifiltp3_gold.zip - Testbench golden waveform , Due ONE week after Part #2 is due (clock speed constraint has been reduced to 20 Mhz for Fall 2002).
Lab 7: Parts #1, #2: Serial Data Transfer , ZIP archive with needed files
Lab 8 : Structural VHDL - take one of your successful implementations for Lab #6 (parts 1,2 or 3) or Lab #7 (part #2) and implement it in 100% VHDL - ie. no schematic capture is allowed.

Lecture Supplements, Spring 2003

In-class Group Exercises on Datapath Scheduling, Spring 2003

Data Sheets

Altera Stratix FPGA
Altera Flex10K FPGA
Altera Max 7000A FPGA
Xilinx Virtex FPGA
Actel MXDS FPGA
Cypress Ultra37000 CPLD
Cypress PAL20 PLD
Cypress PAL22V10 PLD
Texas Instruments Logic Selection Guide , lists all of the low voltage IO families, discussions of them.

Sample Tests

Misc

CRC Faq
CRC Explained... Original source is here

To read PDF documents on the Sun systems, do "swsetup acrobat", then do "acroread documentname".

VHDL Examples

Click HERE for the VHDL examples from the notes. These have checked to work with Altera Maxplus2.

UP1 Board

Professor Jim Hamblen's (Ga Tech) UP1 Board page Look here for interesting project ideas, neat implementations, and miscellaneous tips.
Ga Tech Page that discusses use of Video module and keyboard module for UP1 Board.
Zip file that contains video/keyboard modules referenced above.
Improved keyboard function that has a little better performance (important for large designs if using the onboard 25Mhz clock as system clock for keyboard module. The original module had marginal timing and would sometimes fail if integrated into a larger design.)
Zip archive containing the SOF file for 'circles' game (requires keyboard, VGA monitor). 'Circles' is a Nim variant - instructions for the game are displayed on the video screen. Spring 99 class project.

Using the Altera UP1 Board

Make sure that the jumpers on the board are set correctly. Look at this document for an explanation of the jumpers. Look at pages 5,6 at the description of the jumper settings and make sure that you can program the Flex10K device.
Connect power to your board, and the byteblaster cable to the parallel port and to your board.
Start Maxplus2, and click on the ByteBlaster icon or the "Programmer" choice under the Max+plusII menu. If the Hardware setup window does not appear, then access this via "Options -> Hardware Setup". Choose ByteBlaster, and make sure that LPT1 port is selected. Close the Hardware setup menu.
Under the "JTAG" menu, make sure that "Multi-Device Jtag Chain" is checked. Then under the "JTAG" menu, execute the "Multi-Device JTAG Chain Setup". When this menu pops up, click on "Select Programming File" and browse to the .SOF file that you want to download. Click on "Add", then exit by clicking on "Ok". There should be only ONE programming file selected.
In the "Programmer" popup menu, click on "Configure", and you should see the download completion bar progress from 0% to 100%. Your design is now downloaded.
If you are running NT, you must install the ByteBlaster driver. Access the Multimedia icon under the Control Panel, and add an "Unknown device"; point the installation program at the maxplus2/drivers directory. Choose the "ByteBlaster" when the popup menu appears, and the installation will complete. You will need to reboot. If you are running Win2000 you must follow a similar procedure, but you must have version 9.6 or greater in order to get the ByteBlaster drivers for Win2000. I do not know if the Win2000 drivers will work with WinXP.

Maxplus Oddities, Error Messages

This is a list of common error messages/oddities/errata/weird_stuff that you need to be aware of when using the Maxplus software:

"Error: Input pinstub/port somepin is unconnected and has no default value" -- To locate the problem component, double click on the error message and the component will be highlighted.You may forgotten to connect the pin, or misspelled the label of the net that is connected to the pin. Sometimes, it will look like a net is connected to a pin but it is not actually connected. Try clicking on the net and moving it around - if it is connected, then the net will 'rubberband' and remain connected.
"Error: node missing source :"pinname"[ID:compnum:pinname]" . The pinname is the name of the pin, the compnum is the number of the component (the component number is displayed in the lower left hand corner of the component - the BUF8 picture above has a component number of '16'). This error happens if there is actually a net connected to an input pin, but the net does not connect to an output pin of some other component. The most common cause of this problem is that you have either mislabeled the output input net name or the input pin net name.
"Error: Illegal node or pin name :"pinname"[ID:compnum:pinname]" . This usually happens if an illegal syntax has been used for a bus name, such as A[7:0] or A[7.0], or A(7..0), etc. A bus name uses two periods to seperate the high/low bus indexes, and brackets around the bus indexes ( A[7..0]).
"Error: Width mismatch in pinstub :"pinname"[ID:compnum:pinname]" . This is due to a mismatch between the label on a bus and the pin that it is connecting to. For example, if a bus has the label A[8..0] (9-bits wide), and the pin has the label A[7..0] ( 8 bits wide), this error will be generated. This also happens if you use a single dimensional bus label where a multi-dimensional bus label is required, or vice-versa.
"Error: Tri-state node must be driven by a TRI buffer, but is driven by a primitive :"pinname"[ID:compnum:pinname]" . This happens when you connect mistakenly connect two outputs together by physical connection or by using the same net name (you can only do this if you are using a tri-state buffer, and the FLEX devices we are mapping to do not implement tri-state buffers).
.TDF file extension: When you edit a text file using Maxplus, the default extension is ".TDF". Do NOT use this for a VHDL code - the default compiler invoked on a ".TDF" is not the VHDL compiler. Use a ".vhd" file extension for VHDL files.
VHDL Syntax Errors . In general, try to solve the first error message - this error may have generated many of the other error messages. Also, when you edit a file via the "Max+plus II -> Text Editor", you can use the "Templates-> VHDL Template" menu to insert various templates for VHDL structures. This can save you from many common syntax problems - I would highly suggest that you use this.
Student Edition Installation under Win98: Many people have installed the Student Edition under Win98 with no problems. However, the following problem occurred on a Pentium 130Mhz, 32Mb RAM system running Win98 - everytime the installation procedure was attempted, a system error occurred that would terminate the installation. Many different things were tried, including shutting down all starup programs, copying the "Pc/Maxplus2 directory tree to the C: drive before installation, etc. We finally got it work by first copying the "Pc/" directory on the Maxplus CDROM to drive C:, booting in Safe Mode, and then doing the installation (Safe mode does not have a CDROM driver so that is why the "Pc/" directory had to be copied first). After the installation completed, the machine was booted normally and all worked ok.
Student Edition, "Partitioner Error" Under the Student edition, if a design won't fit (i.e. a 16-bit multiplier in a Max7000 part), then you will occasionally get a 'Internal Partitioner Error' instead of a 'Design does not Fit' message. Try mapping the design to a Flex10K family part.
Student Edition, Synthesis Problem with Finite State Machines, Conditional outputs in Processes. These two files, fsmbad.vhd and fsmgood.vhd illustrate a synthesis problem with the student edition V7.21 (the problem does not occur in the Professional edition). The lecture notes use the style that is shown in the 'bad' example, so be SURE to use the style in the 'good' example if you are using the Student edition. This is actually a symptom of a larger problem as shown by test_bad.vhd and test_good.vhd . In the student edition V7.21, if you have a conditional output in an 'if' statement inside of a CASE statement, the output will have a latch synthesized on it if the 'if' statement does not have an 'else' clause EVEN if the output is previously assigned a default value. The professional edition generates the correct logic (no latch). BE CAREFUL OF THIS!!!! This bug is tough to spot!! Try to avoid conditional outputs inside of case statementts if you are using Student V7.21 or put them in concurrent statements outside of the process.
Here are two more examples that correspond to the FSM defined in the Datapath notes . The first file is the recommended method for writing FSMs if you are using the Student edition V7.21. The second file follows the style discussed in the notes, and works fine with the professional edition.
Student Edition, Compare operation. This is from James Hamblen, Professor at Ga Tech. The only big VHDL problem issue that I have come across deals with '<' or '>' compare ops. It does not select signed correctly and seems to always use unsigned compare operations (i.e. it ignores your signed library statement). This is fixed only in the latest pro version.

Actual Lecture List, Fall 99

August 23rd: Mon, Wed: Comb Logic Review. Fri: Seq Logic Review
Aug 30th: Mon: Maxplus Overview (Lab #1 discussion), Wed, Fri: VHDL Comb Logic, Fixed Point discussion
Sep 6 : Mon: No class, holiday. Wed: Implementation Technlogy, Fri: Fixed Point discussions, Lab #2
Sep 13: Mon:Implementation Tech (overview, no detailed FPGA discussion), Wed: Start System Timing Friday: System Timing, Talk about Lab #4
Sep 20: Monday: Finish System Timing, start Pipelining, Wed: Finish Pipelining, Talk about Lab #5
Sep 27: Monday: Sequential Systems with VHDL, Wed: Ram Zero Dpath example, Test #1 review, Friday: Test #1
Oct 4: Monday: Test #1 Results, FSMs in VHDL, Wed: FSM timing, Implementations of Sync RAM with zeroing Capability
Oct 10: Monday: Altera FPGA Architecture, Wed: Matrix Multiply Assignment, Xilinx/Actel FPGA architectures
Oct 17: Monday: Finish Xilinx/Actel FPGA architectures, Low Voltage IO Families, Wed: DalSemi lecture by Chris Collins
Oct 24: Monday: Discuss class project, Wed: Scheduling, Flowgraphs
Nov 1: Monday: More on scheduling, Wed: Increasing Datapath initiation rate, UP1 Board demo
Nov 8: Monday: Design for Test, Wed: Test #2
Nov 15: Monday: Discussion of Test #2 results, Project speedup hints. Wed: Altera Video Module discussion
Nov 22: Monday: Finished up Altera Video Module, discussed high level synthesis
Nov 29: Review for Test 3, Wed: Test #3
Dec 6: Mon Test #3 results, review for Final

Non-tech topics (Spring 2000)

Sept 13: Difference between Architect, logic designer, circuit designer
Sept 27: Privacy chips vs Law enforcement backdoors
Oct 4: Avoiding Engineering obsolesence
Oct 11: Microsoft a monopoly? Intel a monopoly?
Oct 21: Interviewing, Technical Interviews (Chris Collins, DalSemi)
Nov 3: Intellectual Property.
Nov 8: Time to Market, Product development
Nov 15: Y2K hysteria

Old lectures

Maxplus II overview , PDF file .
Course introduction, Review of Combinational Logic , PDF file .
Review of Sequential Systems , PDF file .
Combinational Logic in VHDL , PDF file .
Fixed Point arithmetic, Saturating adders, Maxplus LPMs
, PDF file .
Implementation Technologies
FPGA Families Summaries.
You should also look at the data sheets.
System Timing Issues , PDF file
Introduction to Pipelining , PDF file
FPGA Timing Models
You should also look at the data sheets.
Altera Timing Model Details
Intro to Sequential Systems in VHDL , PDF file
Finite State Machines in VHDL , PDF file
FSM + Datapath Design , PDF file
Scheduling, Data Flowgraphs , PDF file
Increasing the Initiation Rate of a datapath, scheduling
Introduction to Design For Test , PDF
Spring '00 Project Hints
Some info about Video displays and the Ga Tech Video module , PDF