Introduction To VHDL for Combinational Logic
PPT Slide
VHDL Statements
VHDL Combinational Template
A VHDL Template for Combinational Logic
Majority Gate Example
Majority Gate with Temporary Signals
Majority Gate with when-else statement
Concurrent Versus Sequential Statements
Majority Gate using process block and if statement
Comments on process block model
Use of if-else
Unassigned outputs in Process blocks
Comments on ‘bad’ architecture
Comments on Priority Example
Priority Circuit with just IF statements.
Priority Circuit with when-else statements.
A Bad attempt at a Priority Circuit
Comments on “bad” Priority Circuit
4-to-1 mux with 8 bit Datapaths
Comments on Mux example
4-to-1 Mux using Select Concurrent Statement
4-to-1 Mux using Case Sequential Statement
Logical Shift Left by 1
Logical Shift Left by 1 (better way)
4 Bit Ripple Carry Adder
4 Bit Ripple Carry Model
4 Bit Ripple Carry Model using For Statement
Comments on for-loop statement
Summary
Summary (cont.)
Email: reese@erc.msstate.edu
Home Page: http://www.erc.msstate.edu/~reese
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