Objective:                

The objective of this lab is to introduce the student to a combined FSM and Datapath design problem. This lab is worth 150 pts.  This is a 1-week lab.

To Do:

You are to complete the design for a Synchronous SRAM that has a block transfer capability.  The interface to the 64x8 XFER SRAM is given below:

INPUTS:

clk, reset       Clock and high true asynchronous reset
din[7:0]          Data input bus for SRAM
we                  Write Enable signal
addr[5:0]        Addr Bus
ld_wcnt           load line for Word Count Register
ld_to                load line for TO register
ld_from           load line for FROM register
xfer                  control line that starts block transfer

OUTPUTS:

busy                status output that indicates a TRANSFER operation is in progress
dout[7..0]       Data output bus          

The XFER SRAM has the capability to do a block transfer of WCNT number of bytes from location FROM  to location TO.   Three internal registers are used to hold the values of WCNT, FROM, TO.. The XFER input starts a block transfer;  the BUSY line is high while the transfer is ongoing.  The ranges of FROM and TO can overlap, no range checking is done.  The three internal registers are all loaded from the ADDR bus.

Implementation Guidelines                                                

A good start at the datapath can be found in the xferram.gdf schematic.  Feel free to use this as a starting point; modify it in any way that you desire.  The datapath is missing the FSM block; you must describe your FSM via an ASM chart and implement the FSM in VHDL.

Each byte must transferred in two clock cycles;  one clock cycle for read and one clock cycle for write.

You must remember that the SRAM used in the above schematic is SYNCHRONOUS. On a read, the address bus is latched on the rising clock edge; the data is available after the falling edge and will remain stable for the remainder of the clock cycle.  On a write, the address, data, WE signal is sampled on the rising clock edge.

Testing Your Design                                              

The XFERGOLD.SCF file is a golden waveform file that you can use to test your design.  Examine this waveform closely and make sure that you understand the functionality of the design before you begin your work.  Other files referenced in the schematic are:

buf8.vhd, buf6.vhd, reg8.vhd, reg6.vhd

Before using the XFERRAM.GDF schematic above, compile each of these files so that the symbol is created.

To Turn In

A code listing of the VHDL file for your FSM, the ASM chart for your FSM, and the final schematic.

Check Off                                                      

You must DEMONSTRATE your xferram design to the TA and show that your results matches the expected results.