VHDL is one of popular hardware description languages. There coding examples written by VHDL. They are available to use on Mentor Graphic Falcon Framework in Tokyo Institute of Technology. They are already checked their performance by Logic Simulator Quick VHDL. However there may be several buggs which I cannot detect. Please send e-mail to "tootsuka@de.tokyo-ct.ac.jp" if you find buggs.
| Entity Name | Abstract. |
|---|---|
| ckgen | clock generator |
| d-ff | d flip flop ( 74LS74 ) |
| ls138 | 3 to 8 demultiplexer |
| ls139 | dual 2 to 4 demultiplexer |
| ls153 | dual 4 to 1 data selector |
| ls163 | syncronous 4 bit counter |
| ls169 | syncronous up/down counter |
| ls175 | quad d-ffs |
| ls181 | arithmatic logic unit |
| Entity Name | Abstract. |
|---|---|
| bufif1_0 | 3 state buffer if 1 with no delay |
| bufif1_5 | 3 state buffer if 1 with 5 ns delay |
| bufif0_0 | 3 state buffer if 0 with no delay |
| bufif0_5 | 3 state buffer if 0 with 5 ns delay |
| notif1_0 | 3 state inverter if 1 with no delay |
| notif1_5 | 3 state inverter if 1 with 5 ns delay |
| notif0_0 | 3 state inverter if 0 with no delay |
| notif0_5 | 3 state inverter if 0 with 5 ns delay |
| ls194 | 4 bits shift register |
| ls257 | quadruple 2 line to 1 line data selector/multiplexers |
| ls374 | octal 3 state d-ffs |
| Entity Name | Abstract. |
|---|---|
| ls152 | 8 to 1 data selector |
| ls377 | 8 bit d-ffs |
| ls540 | octal 3 state buffer ( inverted ) |
| ls541 | octal 3 state buffer |
| ls157 | quad 2 to 1 data selector |
| ls04 | inverter |
| ls00 | nand |
| ls02 | nor |
| ls08 | and |
| ls32 | or |
| ls10 | 3 inputs nand |
| ls11 | 3 inputs and |
| ls27 | 3 inputs nor |
| ls20 | 4 inputs nand |
| ls21 | 4 inputs and |
| ls30 | 8 inputs nand |
| Entity Name | Abstract. |
|---|---|
| hadd.hdl | half adder ( possible to synthesize ) |
| dff1.hdl | D Flip-Flop (No.1) TTL 7474 ( possible to synthesize ) |
| dff2.hdl | D Flip-Flop (No.2) ( possible to synthesize ) |
| multi_p.vhd | 8 Bit Multiplier |
| Entity Name | Abstract. |
|---|---|
| hadd.hdl | half adder ( possible to synthesize ) |
| cpu_package.hdl | Package file for EX1 |
| bu.hdl | Bus Unit of EX1 |
| cg.hdl | 2 Phase Clock Generator of EX1 |
| cu.hdl | Control Unit of EX1 ( possible to synthesize ) |
| eu.hdl | Execution Unit of EX1 ( possible to synthesize ) |
| iou.hdl | I/O Unit of EX1 |
| mu.hdl | Memory Unit of EX1 |
| ru.hdl | Register Unit of EX1 ( possible to synthesize ) |
| rf.hdl | Flip-Flops for Run Switch and Reset Switch of EX1 ( possible to synthesize ) |
| ex.hdl | 8 bit Simple Microprocessor EX1 ( for student experiments in T.I.Tech. ) |