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-- Copyright Mentor Graphic Corporation 1991. 
-- All rights reserved.  
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--
--  Model Title:  registor unit
--  Date Created: 94/09/16 (Fri)
--  Author:       T.Ohtsuka ( tootsuka@ss.titech.ac.jp)
--
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-- Model Description: 
--
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--
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_1164_EXTENSIONS.ALL ;

-- LIBRARY my_packages ;
-- USE my_packages.cpu_package.ALL ;

ENTITY ru IS
   PORT (
         acc_lsb        :  OUT   STD_ULOGIC ;
         clk1           :  IN    STD_ULOGIC ;
--         clk2           :  IN    STD_ULOGIC ;
         init           :  IN    STD_ULOGIC ;
         alubu          :  IN    STD_ULOGIC_VECTOR(7 DOWNTO 0) ;
         carry          :  IN    STD_ULOGIC ;
         zero           :  IN    STD_ULOGIC ;
         pc_out            :  IN    STD_ULOGIC ;
         sp_out            :  IN    STD_ULOGIC ;
         acc_out        :  IN    STD_ULOGIC ;
         pc_load        :  IN    STD_ULOGIC ;
         sp_load        :  IN    STD_ULOGIC ;
         acc_load       :  IN    STD_ULOGIC ;
         if_carry       :  IN    STD_ULOGIC ;
         if_zero        :  IN    STD_ULOGIC ;
         rotate_right      :  IN    STD_ULOGIC ;
         rotate_left    :  IN    STD_ULOGIC ;
         shift_right    :  IN    STD_ULOGIC ;
         shift_left        :  IN    STD_ULOGIC ;
         a              :  OUT   STD_ULOGIC_VECTOR(7 DOWNTO 0) ;
         acc_msb        :  OUT   STD_ULOGIC ;
         zfc_acc        :  OUT   STD_ULOGIC
        ) ;
END ru ;

-- ---------------------------------------------------------
--Copyright Mentor Graphic Corporation 1991.
--All rights reserved.
-- ---------------------------------------------------------
--Arch. Body for entity declared in 
------------------------------------------------------------
--
 
ARCHITECTURE behav1 OF ru IS

--SIGNAL   rsl_ctl : STD_ULOGIC_VECTOR(4 DOWNTO 0) ;
--SIGNAL   a_pc,a_sp,a_acc : STD_ULOGIC_VECTOR(7 DOWNTO 0) ;
SIGNAL   pc,sp,acc : STD_ULOGIC_VECTOR(7 DOWNTO 0) ;

BEGIN

  pc_process : PROCESS(clk1) --,init,pc_load,pc_out,if_carry,if_zero)
--  VARIABLE  pc :   STD_ULOGIC_VECTOR(7 DOWNTO 0) ;    -- program counter registor

  BEGIN
   IF ((clk1='1') AND (clk1'LAST_VALUE='0') AND clk1'EVENT ) THEN
      IF (init = '1') THEN
         pc <= "00000000" ;
      END IF ;
      IF (pc_load = '1') THEN
         pc <= alubu ;
      END IF ;
      IF (if_carry = '1' AND carry = '1' ) THEN
         pc <= alubu ;
      END IF ;
      IF (if_zero = '1' AND zero = '1') THEN
         pc <= alubu ;
      END IF ;
--      IF pc_out = '1' THEN
--         a_pc <= pc ;
--      END IF ;
   END IF ;
  END PROCESS pc_process ;

  sp_process : PROCESS(clk1) --,sp_out,sp_load)
--  VARIABLE  sp :   STD_ULOGIC_VECTOR(7 DOWNTO 0) ;    -- stack pointer resistor

  BEGIN
   IF ((clk1='1') AND (clk1'LAST_VALUE='0') AND clk1'EVENT ) THEN
      IF (sp_load = '1') THEN
         sp <= alubu ;
      END IF ;
--      IF sp_out = '1' THEN
--         a_sp <= sp ;
--      END IF ;
   END IF ;
  END PROCESS sp_process ;

  acc_process : PROCESS(clk1) --,acc_load,acc_out,rsl_ctl)
--  VARIABLE  acc :  STD_ULOGIC_VECTOR(7 DOWNTO 0) ;   -- accumlator
    VARIABLE   rsl_ctl : STD_ULOGIC_VECTOR(4 DOWNTO 0) ;

  BEGIN
   IF ((clk1='1') AND (clk1'LAST_VALUE='0') AND clk1'EVENT ) THEN
      rsl_ctl := rotate_right & rotate_left & shift_right & shift_left & acc_load;
      CASE rsl_ctl IS
         when "10000"   => 
            acc <= carry & acc(7 DOWNTO 1) ;
         when "01000"   => 
            acc <= acc(6 DOWNTO 0) & carry;
         when "00100"   => 
            acc <= "0" & acc(7 DOWNTO 1) ;
         when "00010"   => 
            acc <= acc(6 DOWNTO 0) & "0" ;
         when "00001"   => 
            acc <= alubu ;
         when OTHERS    => NULL ;
      END CASE ;
--      IF acc_out = '1' THEN
--         a_acc <= acc ;
--      END IF ;
   END IF ;
  END PROCESS acc_process;

  high_imp_out : PROCESS(pc_out,sp_out,acc_out, pc, sp, acc)
  BEGIN
      IF (pc_out = '1' AND sp_out = '0' AND acc_out = '0') THEN
         a <= pc ;
      ELSIF ( pc_out = '0' AND sp_out = '1' AND acc_out = '0') THEN
         a <= sp ;
      ELSIF ( pc_out = '0' AND sp_out = '0' AND acc_out = '1') THEN
         a <= acc ;
      ELSE
         a <= "ZZZZZZZZ" ;
      END IF ;
  END PROCESS high_imp_out ;
      acc_msb <= acc(7) ;
      acc_lsb <= acc(0) ;
      zfc_acc <= (rotate_right AND NOT ( carry OR acc(7) OR acc(6) OR acc(5) OR acc(4) OR acc(3) OR acc(2) OR acc(1) ))
           OR (rotate_left AND NOT (acc(6) OR acc(5) OR acc(4) OR acc(3) OR acc(2) OR acc(1) OR acc(0) OR carry ))
           OR (shift_right AND NOT (acc(7) OR acc(6) OR acc(5) OR acc(4) OR acc(3) OR acc(2) OR acc(1) ))
           OR (shift_left AND NOT (acc(6) OR acc(5) OR acc(4) OR acc(3) OR acc(2) OR acc(1) OR acc(0) ))
           OR (acc_load AND NOT (alubu(7) OR alubu(6) OR alubu(5) OR alubu(5) OR alubu(4) OR alubu(4) OR alubu(3)
               OR alubu(2) OR alubu(1) OR alubu(0) )) ;

END behav1 ;