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-- Copyright Mentor Graphic Corporation 1991. 
-- All rights reserved.  
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--
--  Model Title:  bus unit
--  Date Created: 95/10/29 (Sun)
--  Author:       T. Ohstuka ( tootsuka@ss.titech.ac.jp )
--
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-- Model Description: 
--
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--

LIBRARY work ;
-- USE work.cpu_package.ALL ;

LIBRARY IEEE,ARITHMETIC ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE ARITHMETIC.STD_LOGIC_ARITH.ALL ;

ENTITY bu IS
   PORT (
         alubu     :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;      -- the result sended to RU
         iob       :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;      -- I/O data that is written
         ir        :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;      -- for the instruction fetch
         mwr       :  IN    STD_LOGIC ;   -- ALU output enable signal from CU
         wp        :  IN    STD_LOGIC ;   -- Memory write signal form IOU
         mrd       :  IN    STD_LOGIC ;   -- Memory read signal form CU
         alu       :  IN    STD_LOGIC_VECTOR(7 DOWNTO 0) ;   -- the result sended from ALU
         data      :  INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) BUS ;   -- bidirectional data port
         dsw       :  IN    STD_LOGIC_VECTOR(7 DOWNTO 0) ;   -- I/O data that are read
         adr       :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;   -- address output for MU
         b         :  OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ;   -- sended to input port B of the ALU
         active    :  IN    STD_LOGIC     -- active signal
        ) ;
END bu ;

-- ---------------------------------------------------------
--Copyright Mentor Graphic Corporation 1991.
--All rights reserved.
-- ---------------------------------------------------------
--Arch. Body for entity declared in 
------------------------------------------------------------
--

LIBRARY IEEE ;
LIBRARY work ;

USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_1164_EXTENSIONS.ALL ; 
-- USE work.cpu_package.ALL ;

ARCHITECTURE behav1 OF bu IS

SIGNAL dbus,data0 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
SIGNAL bus_ctl : STD_LOGIC_VECTOR(2 DOWNTO 0) ; -- bus control 
SIGNAL b_ctl   : STD_LOGIC_VECTOR(1 DOWNTO 0) ; -- b port of ALU output control
SIGNAL oe      : STD_LOGIC ; -- output enable of RAM

BEGIN

  bus_ctl <= oe & mwr & wp ;
  oe <= ( mrd OR ((NOT active) AND (NOT wp))) ;
  b_ctl <= mrd & active ;
  WITH bus_ctl SELECT
    dbus <= data0 WHEN "100",
                 -- "data" from RAM is connected
            alu         WHEN "010",
                 -- "alu" from ALU output is connected to write RAM
            dsw         WHEN "001",
                 -- "dsw" from SW is connected to write RAM
            "ZZZZZZZZ"  WHEN OTHERS ;
  iob <= dbus ;
         -- data transfer from dbus to iob ( i/o buffer )
  ir  <= dbus ; 
         -- data transfer from dbus to ir ( instruction resistor )
  alubu <= alu ;
  adr <= alu ;
  WITH bus_ctl SELECT
    data0 <= alu  WHEN "010",
             dsw  WHEN "001",
             dsw  WHEN "011",
                 -- DBUS is connected to RAM
            "ZZZZZZZZ" WHEN OTHERS ;
  WITH b_ctl SELECT
    b <= dbus       WHEN "11",
         -- DBUS is connected to B port of ALU
         "11111111" WHEN OTHERS ;

  WITH bus_ctl SELECT
    data0 <= data WHEN "100",
             "ZZZZZZZZ" WHEN OTHERS ;

  dbustoram : BLOCK(bus_ctl="010" OR bus_ctl="001")
  BEGIN
    data <= guarded data0 ;
  END BLOCK dbustoram ;

END behav1 ;