LIBRARY ieee;

USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


ENTITY multi_p IS
	PORT(
		x,y	: IN  std_logic_vector( 7 downto 0 );
		z	: OUT std_logic_vector( 15 downto 0 )
	);
END multi_p;


ARCHITECTURE dataflow OF multi_p IS

SIGNAL p0	: std_logic_vector( 14 downto 0 );
SIGNAL p1	: std_logic_vector( 14 downto 0 );
SIGNAL p2	: std_logic_vector( 14 downto 0 );
SIGNAL p3	: std_logic_vector( 14 downto 0 );
SIGNAL p4	: std_logic_vector( 14 downto 0 );
SIGNAL p5	: std_logic_vector( 14 downto 0 );
SIGNAL p6	: std_logic_vector( 14 downto 0 );
SIGNAL p7	: std_logic_vector( 14 downto 0 );

BEGIN

	z		<=	p0 + p1 + p2 + p3 + p4 + p5 + p6 + p7;

	PROCESS( x,y )

	BEGIN

		IF( y( 0 ) = '1' ) THEN

				p0	<=	"0000000" & x( 7 downto 0 );

		ELSE

				p0	<=	"000000000000000";

		END IF;

		IF( y( 1 ) = '1' ) THEN

				p1	<=	"000000" & x( 7 downto 0 ) & "0";

		ELSE

				p1	<=	"000000000000000";

		END IF;

		IF( y( 2 ) = '1' ) THEN

				p2	<=	"00000" & x( 7 downto 0 ) & "00";

		ELSE

				p2	<=	"000000000000000";

		END IF;

		IF( y( 3 ) = '1' ) THEN

				p3	<=	"0000" & x( 7 downto 0 ) & "000";

		ELSE

				p3	<=	"000000000000000";

		END IF;

		IF( y( 4 ) = '1' ) THEN

				p4	<=	"000" & x( 7 downto 0 ) & "0000";

		ELSE

				p4	<=	"000000000000000";

		END IF;

		IF( y( 5 ) = '1' ) THEN

				p5	<=	"00" & x( 7 downto 0 ) & "00000";

		ELSE

				p5	<=	"000000000000000";

		END IF;

		IF( y( 6 ) = '1' ) THEN

				p6	<=	"0" & x( 7 downto 0 ) & "000000";

		ELSE

				p6	<=	"000000000000000";

		END IF;

		IF( y( 7 ) = '1' ) THEN

				p7	<=	x( 7 downto 0 ) & "0000000";

		ELSE

				p7	<=	"000000000000000";

		END IF;

	END PROCESS;

END dataflow;