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-- Copyright Mentor Graphic Corporation 1991. 
-- All rights reserved.  
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--
--  Model Title:  control unit
--  Date Created: 95/10/29 (SUN)
--  Author:       T. Ohstuka ( tootsuka@ss.titech.ac.jp )
--
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-- Model Description: 
--
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--
LIBRARY IEEE,ARITHMETIC ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE ARITHMETIC.STD_LOGIC_ARITH.ALL ;

LIBRARY work ;
USE work.cpu_package.ALL ;

ENTITY rf IS
   PORT (
          clk1          :  IN    STD_LOGIC ; -- phase I clock
          init          :  IN    STD_LOGIC ; -- init 
          start         :  IN    STD_LOGIC ; -- start
          halt          :  IN    STD_LOGIC ; -- halt
          last_cycle    :  IN    STD_LOGIC ; -- last cycle of the instruction
          stop          :  IN    STD_LOGIC ; -- stop
          rff           :  OUT   STD_LOGIC   -- output of run FF
        ) ;
END rf ;
-- ---------------------------------------------------------
--Copyright Mentor Graphic Corporation 1991.
--All rights reserved.
-----------------------------------------------------------
--Arch. Body for entity declared in 
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LIBRARY IEEE,ARITHMETIC ;
LIBRARY work ;

USE IEEE.STD_LOGIC_1164.ALL ;
USE ARITHMETIC.STD_LOGIC_ARITH.ALL ;
USE work.cpu_package.ALL ;

ARCHITECTURE behav1 OF rf IS

BEGIN

rff_process : PROCESS(start,clk1)
  -- process of the run FF
  BEGIN

  IF Sw_rising(start) THEN
      -- set run FF
      rff <= '1' ;
  END IF ;

  IF P_rising(clk1) THEN
     IF ( (( halt = '1') AND (last_cycle = '1')) OR ( stop = '1' ) OR ( init ='1' ) ) THEN
       -- reset run FF
       rff <= '0' ;
     END IF ;
  END IF ;

  END PROCESS rff_process ;
END behav1 ;