| Pins: assigned |
Finds all user-entered assigned input, output, and bidirectional pin names in your design file(s) that were successfully extracted from the Current Assignments netlist by the Database Builder. |
| Pins: unassigned |
Finds all user-entered unassigned input, output, and bidirectional pin names in your design file(s) that were successfully extracted from the Current Assignments netlist by the Database Builder. |
| Pins: all |
Finds all user-entered input, output, and bidirectional pin names in your design file(s) that were successfully extracted from the Current Assignments netlist by the Database Builder. |
| Pins: virtual |
Finds all Virtual Pin names in the Last Compilation netlist. |
| Registers: pre-synthesis |
Finds all user-entered register names in your design file(s) that were successfully extracted from the Last Compilation netlist by the Database Builder. |
| Registers: post-fitting |
Finds all user-entered register names in your design file(s) that survived fitting and were successfully extracted from the Last Compilation netlist by the Database Builder. |
| Design Entry (all names) |
Finds all user-entered names in your design file(s) that were successfully extracted from the Last Compilation netlist by the Database Builder. |
| Post-Compilation |
Finds all user-entered and compiler-generated names in the Last Compilation netlist that do not have location assignments and survived fitting. |
| SignalTap® II: pre-synthesis |
Finds all internal device nodes in the pre-synthesis Last Compilation netlist that can be analyzed by the SignalTap II Logic Analyzer. |
| SignalTap II: post-fitting |
Finds all internal device nodes in the post-fitting Last Compilation netlist that can be analyzed by the SignalTap II Logic Analyzer. |
| SignalProbe™ |
Finds all SignalProbe device nodes in the post-fitting Last Compilation netlist. |
