Procedures

Commands

See Also

You can use the Synopsys^® PrimeTime software to perform a timing verification of a Verilog Output File (.vo) or VHDL Output File (.vho) after compilation with the Quartus^® II software. The Quartus II software also generates a TCL Script File (.tcl), which sets up the PrimeTime environment for performing a timing verification.

The following steps describe the typical flow for to perform a timing verification with the PrimeTime software:

1. Set Up the PrimeTime Working Environment

2. Perform a Timing Verification with the PrimeTime Software

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