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Specifies the following options for optimizing netlists during fitting:
| Automatically duplicate logic elements | Directs the Quartus® II software to duplicate logic elements during fitting to increase performance. Only LUTs are duplicated by this option's algorithm; however, the Quartus II software does not duplicate LUTs that are packed with virtual I/Os. This option is often used with the Perform logic element level LUT resynthesis option described below. The Duplicate Logic Elements section of the Compilation Report window lists the duplicated logic elements. For more information about automatically duplicating logic elements, see Application Note 198 (Timing Closure with the Quartus II Software). |
| Perform logic element level LUT resynthesis | Directs the Quartus II software to duplicate logic elements (LUTs only) and resynthesize the LUTs during fitting to increase performance. This option is often used with the Automatically duplicate logic elements option described above. The Logic Element Level LUT Resynthesis section of the Compilation Report window lists the duplicated and resynthesized LUTs. |
These options are available for Cyclone™, Stratix™, and Stratix™ GX devices only. Also, the Quartus II software does not perform netlist optimizations on any node or entity for which you set the Never Allow setting in the Netlist Optimizations logic option.
The Quartus II software cannot perform these netlist optimizations on a back-annotated design. In addition, if you use one or both of these netlist optimizations on a design, and then back-annotate the design, you must generate a Verilog Quartus® Mapping File (.vqm) that indicates the duplicated LUTs that the Quartus II software generated and/or resynthesized while fitting the design.
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Because the Quartus II software duplicates and resynthesizes LUTs only for the current fit of the design, you should not generate a VQM File for the design unless you intend to back-annotate the design with its current fit. |
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