SAR CASE STUDY

Abstract

The Rapid Prototyping of Application-Specific Signal Processors (RASSP) program, a DARPA/Tri-Service four year initiative, has dramatically improved how large complex digital signal processing (DSP) systems are designed, manufactured, upgraded, and maintained. A major program goal was to reduce by at least a factor of four the time from design concept to fielded prototype. Other goals included life cycle cost reduction and quality improvement. Design exercises, or benchmarks, were undertaken to assess RASSP process improvements during the four year program. This case study provides a summary of the first benchmark used to measure progress toward these 4X goals. It describes what was done, what benefits were demonstrated, and the lessons we learned to improve the RASSP design process.

The first benchmark, the design and prototyping of a real-time processor for a Synthetic Aperture Radar (SAR) defined by MIT Lincoln Laboratory demonstrated the adaptability and flexibility achievable by using the RASSP methodology and design environment. The substantial computational throughput (1.6 Gops), memory (80Mbytes), bandwidth (80Mbytes/sec), 2x expandability for future algorithm enhancements, optical interface, size, weight and environmental requirements of the SAR processor made it a realistic application vehicle for benchmarking and demonstrating the RASSP design process. Using first year RASSP concepts and tools, the ATL RASSP benchmark project demonstrated a1.7X overall reduction in time-to-market and a 1.3X reduction in development cost compared to traditional developments. In a follow up effort, real-time application software development time was reduce by 7X and development cost decrease by 4x was demonstrated through the use of the second year RASSP auto coding tool suite. This resulted in an overall 2.6X reduction in time-to-market when interpolated with the original schedule.

The ATL approach for achieving the RASSP program goals was based on implementing three technology thrusts: infrastructure, Methodology and Model Year Architectecture

Purpose

This case study describes the development of the synthetic aperture radar (SAR) image processor using the Lockheed Martin Advanced Technology Laboratories RASSP design environment. Results from using executable specifications; parametric cost estimating tools; VHDL-based performance modeling for architecture tradeoffs; hardware/software codesign; virtual prototyping for architecture verification; software generated by autocode technology; and VHDL-based, top-down hardware development are shown. Using the description of the overall process methodology developed for RASSP, as applied to the SAR processor, the highlights of the implementation strategy and the lessons learned are presented.

Roadmap

1.0 Executive Summary

1.1 SAR Benchmark Summary
1.2 RASSP Process
- 1.2.1 System Design
- 1.2.2 Architecture Design
- 1.2.3 Detail Design
- 1.2.4 Integration and Test

2.0 SAR Problem Overview

2.1 SAR System
2.2 SAR Processing Algorithms
2.3 Form Factor Contraints
2.4 Accuracy
2.5 Latency
2.6 Data Interfaces
2.7 Control and Diagnostic Interface
2.8 Summary

3.0 System Design

3.1 System Process Description
- 3.1.1 RASSP Innovations in the System Design Process
3.2 System Requirements Analysis
- 3.2.1 Executable Specification
3.3 Functional Analysis
3.4 System Partitioning
3.5 Lessons Learned in the System Design of the SAR Benchmark
- 3.5.1 Executable Specification
- 3.5.2 System Tools

4.0 Architecture Design

4.1 Architecture Process Descripion
- 4.1.1 RASSP Innovations in the Architecture Design Process
4.2 Functional Design
- 4.2.1 Architecture Sizing of SAR Algorithm
- 4.2.2 Flow Graph Generation
- 4.2.3 Develop Command Program
4.3 Architecture Selection
- 4.3.1 Initial Size, Weight and Power
- 4.3.2 Architecture Definition
- 4.3.3 Performance Modeling
- 4.3.4 Architecture Trade-off Analysis
4.4 Architecture Verification
- 4.4.1 Abstract Behavior Simulation
- 4.4.2 Autocode Generation
4.5 Lessons Learned In the Architecture Design of the SAR Benchmark
- 4.5.1 Hierarchical Simulation (Performance Modeling)
- 4.5.2 Hierarchical Simulation (Abstract Behavior)
- 4.5.3 Autocoding Software

5.0 Detailed Design

5.1 Detailed Design Process Description
- 5.1.1 RASSP Innovations in the Detailed Design Process
5.2 DATA I/O Module Design Process
- 5.2.1 Detailed Behavioral/RTL Modeling
- 5.2.2 Detailed Board Design Process
- 5.2.3 FPGA Design Process
- 5.2.4 Fabricate and Assemble Data I/O Module
5.3 Lessons Learned in Detailed Design

6.0 Integration and Test

6.1 Integration and Test Process Description
6.2 Integration and Test
6.3 Document Update
6.4 Acceptance Test
6.5 Lessons Learned in Integration and Test
- 6.5.1Virtual Prototype
- 6.5.2 Design for Testability
- 6.5.3 Test and Integration Environment

7.0 Conclusions

8.0 Acronym List

9.0 Glossary

10.0 References

10.1 Application Notes
10.2 Articles / Presentations

A Appendix

A.1 Introduction to Data-Flow Methodology
- A.1.1 Control Driven Versus Data Driven Computing
- A.1.2 Data Flow Design
A.2 Autocoding the Synthetic Aperture Radar (SAR) Using GEDAE™
- A.2.1 Building the SAR Application
- A.2.2 Running the Graph
- A.2.3 Distributing or Embedding the Graph