SAR Case Study

The benchmark demonstrated a top-down design process that moved from executable specification, to performance model, to abstract behavior model, to detail behavior model and synthesizable, register-transfer level using executable models written in VHSIC Hardware Description Language. The use of hierarchical virtual prototyping minimized design errors and design time by verifying hardware/ software components before manufacturing. The physical prototype of the SAR processor with a mix of custom and commercial, off-the-shelf (COTS) hardware/ software components was built and quickly integrated with first-pass design success that passed all performance requirements.

Performance models were used to quickly simulate various mixtures of custom and COTS hardware with numerous software mappings of the SAR algorithm during architecture trade-offs. Originally, an ADSP21060-based COTS board was chosen for the design; however, delay in the delivery of a fully functional digital-signal-processor component forced a late change to i860-based COTS boards. Due to the previously completed performance modeling during the architecture trade-offs, the new mapping configuration of the software and amount of hardware and memory configurations were already known, so a quick change was possible.

The SAR benchmark demonstrated a new technique using data -flow graphs of the algorithm for quick development of efficient, real-time, embedded, application code. The overall development time for the real-time application software was reduced by a factor of seven and the development cost was decreased by a factor of four. The processing efficiency of the autocoded software was only 10 percent less than manually-optimized code.