SAR Case Study

The program used design benchmarks to assess process improvements. This case study summarizes the first benchmark, describing tasks, demonstrated benefits, and lessons learned. The results of the benchmark were significant, including independently verified reductions in cycle time of 40 percent and reductions in software development time by a factor of seven.

• Substantial computational throughput (1.6 GFLOPS)
• Memory (80 Mbytes)
• Input/output bandwidth (80 Mbytes/sec)
• 2X expandability for future algorithm enhancements
• Fiber-optic interface
• Size and weight
• Environmental requirements.

The benchmark's goal was to demonstrate the adaptability and flexibility achievable using RASSP's methodology and design environment. Using first-year RASSP concepts and tools, Lockheed Martin Advanced Technology Laboratories (LM ATL) demonstrated the following improvements as compared to traditional processes and as authenticated by MIT/LL:

• 1.7X overall reduction in time-to-prototype
• 1.3X reduction in development cost.

Using the second-year RASSP autocoding tool suite for real-time application software development, LM ATL demonstrated the following improvements as compared to traditional processes:

• 7X reduction in development time of real-time application software development
• 4X reduction in development cost of real-time application software development.

The overall improvement using the RASSP design process was a 2.6X reduction in time-to- prototype

Lockheed Advanced Technology Laboratories' team used tools that helped requirement capture and analysis; functional design; and cost, reliability, availability, and maintainability analysis. Cost analysis evaluated life-cycle and development costs for the SAR system. The team accomplished in less than two labor months SAR's system requirement capture, analysis, and partitioning. This resulted in hardware and software module specifications that were generated automatically from a single complete, consistent, and traceable database.

The RASSP SAR benchmark demonstrated a top-down design process that moved from an Executable Specification, through performance modeling, to a full behavioral virtual prototype using models written in a single language (VHDL).

• COTS ADSP21060-based DSP Modules for most of SAR's processing
• Custom module for data input and output
• Custom module for Finite Impulse Response (FIR) filtering
• COTS single-board computer for control
• COTS-based backplane for communication among modules.

The study produced an abstract behavioral description of the hardware/software architectural elements that ensured interoperability early in the design process.

The Team captured SAR's design in a single-language (VHDL), hierarchical virtual prototype. It used the prototype to verify design performance from the initial concept of the multiprocessor system through synthesizable Register Transfer Level (RTL) descriptions. This allowed the algorithm's performance to be verified and the required DSP harware to be determined before purchasing or designing and hardware.The use of a single language enabled the Team to add more fidelity to the virtual prototype as the design progressed and as perceived risk indicated. High-risk areas were modeled at lower levels of abstraction, while low risk areas were modeled at higher levels of abstraction.

The Team optimized the mix of COTS and custom hardware to gain a significant cost and size advantage over an all- COTS implementation. A custom interface and a FIR filter module easily integrated with COTS DSP Modules through a COTS backplane, which used a standard interface. This combination provided a smaller and cheaper solution than either an all-COTS or custom-equipment approach. The industry standard interfaces and autocoding software development tools provided an upgrade path that continually reduced support costs through model-year upgrades.

RASSP's autocoding tools were initially unavailable for the SAR benchmark, so software development and coding were done manually. When the tools became available six months later, after successful completion of SAR acceptance test, the team generated application code from the data flow-graph description of the required signal- processing algorithm and mapped the code to the architecture. Compared to manual coding, autocoding reduced application development time by 7X and development cost by 4X, and the improvements included the time to learn the tools. The autocoded software generated using the beta version of the autocoding tools was within 10 percent of the processor's efficiency of the manually generated and optimized code. The Team also improved software productivity by successfully elevating the level of abstraction, at which most design and development work occurs, and by eliminating the need for a large programming team. The combination of graphical program specification and autocoding allowed the designer to concentrate on meeting system-level design requirements and minimized the designer's need to track low-level details of interprocessor communications and memory management.

It is typical to consider emerging technologies during a development effort. The COTS AD21060 (SHARC)-based DSP Module was such an emerging technology but it was unavailable when the Team needed it. Because of the earlier architecture design study, the team quickly chose the alternative COTS i860 based DSP product without a substantial loss of time and effort.

• Those caused by the layout tool for the custom FPGA circuits
• Those in manually-generated software, where the programmer did not follow the exact software mappings of the performance simulations
• Those in specialized test equipment supplied by the government

The team used the virtual prototype to diagnose the defects with the following results:

• Enhanced Fault Finding/Troubleshooting - The SAR custom Data I/O Module has two daughter cards that prevented significant probing during integration. As a result, the Team used the virtual prototype to determine if hardware failure, design flaws, or simple misunderstandings were the cause of unexpected behavior. The Team found a vendor's documentation mistake when the hardware and virtual prototype behavior did not match. Without the virtual prototype, the Team would have wasted a significant amount of time searching for non-existent design flaws. Instead, a simple correction was quickly identified and implemented.
• Accelerated Hardware Integration - The team completed the testing of the two custom modules and integration them with various COTS hardware in two weeks instead of the normal four weeks or more.
• Accelerated Hardware/Software Integration - The SAR software/hardware integrated and test time fell to one month from the normal three months for over 10,000 source lines of application and command code, thousands of lines of code for diagnostics and test code, and two COTS operating systems.

The SAR processor passed the formal acceptance test conducted by MIT/LL and met all specifications.

This case study describes the RASSP experience early in the program. The methodology document and other case studies and applications notes on this web site provide further information on the RASSP methodology.