mti_GetArraySignalValue()

Gets the value of a VHDL signal of type array.

Syntax

value = mti_GetArraySignalValue( signal_id, buffer ) 

Returns

Name	Type	Description
value	void *	A pointer to the value of the specified signal

Arguments

Name	Type	Description
signal_id	mtiSignalIdT	A handle to a VHDL signal of type array
buffer	void *	A buffer into which the value is to be placed; OPTIONAL - can be NULL

Description

mti_GetArraySignalValue() returns the value of an array-type signal.

If the buffer parameter is NULL, then mti_GetArraySignalValue() allocates memory for the value and returns a pointer to it. The caller is responsible for freeing the returned pointer with mti_VsimFree(). If the buffer parameter is not NULL, then mti_GetArraySignalValue() copies the value into the buffer parameter and also returns a pointer to it. The appropriate length of the buffer parameter can be determined by calling mti_TickLength() on the type of the array signal.

The array value is interpreted as follows:

For a subelement of type	The value should be cast to
Enum	(char *) if <= 256 values (mtiInt32T *) if > 256 values
Physical	(mtiInt32T *)
Real	(double *)
Scalar (Integer)	(mtiInt32T *)
Time	(mtiTime64T *)

Related functions

mti_GetSignalValue()

mti_GetSignalValueIndirect()

Example

FLI code

#include <mti.h>

typedef struct signalInfoT_tag {
  struct signalInfoT_tag * next;
  char                   * name;
  mtiSignalIdT             sigid;
  mtiTypeIdT               typeid;
} signalInfoT;

typedef struct {
  signalInfoT   * sig_info;     /* List of signals. */
  mtiProcessIdT   proc;         /* Test process id. */
} instanceInfoT;

static void printValue( mtiSignalIdT sigid, mtiTypeIdT sigtype, int indent )
{
  switch ( mti_GetTypeKind(sigtype) ) {
   case MTI_TYPE_ENUM:
   case MTI_TYPE_PHYSICAL:
   case MTI_TYPE_SCALAR:
    { 
     mtiInt32T scalar_val;
     scalar_val = mti_GetSignalValue( sigid );
     mti_PrintFormatted( "  %d\n", scalar_val );
    }
    break;
   case MTI_TYPE_ARRAY:
    {
     int            i;
     mtiInt32T      num_elems;
     mtiTypeIdT     elem_type;
     mtiTypeKindT   elem_typekind;
     void         * array_val;

     array_val = mti_GetArraySignalValue( sigid, 0 );
     num_elems = mti_TickLength( sigtype );
     elem_type = mti_GetArrayElementType( sigtype );
     elem_typekind = mti_GetTypeKind( elem_type );
     switch ( elem_typekind ) {
      case MTI_TYPE_ENUM:
       {
        char ** enum_values;
        enum_values = mti_GetEnumValues( elem_type );
        if ( mti_TickLength( elem_type ) > 256 ) {
         mtiInt32T * val = array_val;
         for ( i = 0; i < num_elems; i++ ) {
          mti_PrintFormatted( "  %s", enum_values[val[i]] );
         }
        } else {
         char * val = array_val;
         for ( i = 0; i < num_elems; i++ ) {
          mti_PrintFormatted( "  %s", enum_values[val[i]] );
         }
        }
       }
       break;
      case MTI_TYPE_PHYSICAL:
      case MTI_TYPE_SCALAR:
       {
        mtiInt32T * val = array_val;
        for ( i = 0; i < num_elems; i++ ) {
         mti_PrintFormatted( "  %d", val[i] );
        }
       }
       break;
      case MTI_TYPE_ARRAY:
       mti_PrintMessage( "  ARRAY" );
       break;
      case MTI_TYPE_RECORD:
       mti_PrintMessage( "  RECORD" );
       break;
      case MTI_TYPE_REAL:
       {
         double * val = array_val;
         for ( i = 0; i < num_elems; i++ ) {
          mti_PrintFormatted( "  %g", val[i] );
         }
       }
       break;
      case MTI_TYPE_TIME:
       {
         mtiTime64T * val = array_val;
         for ( i = 0; i < num_elems; i++ ) {
          mti_PrintFormatted( "  [%d,%d]",
                             MTI_TIME64_HI32(val[i]),
                             MTI_TIME64_LO32(val[i]) );
         }
       }
       break;
      default:
       break;
     }
     mti_PrintFormatted( "\n" );
     mti_VsimFree( array_val );
    }
    break;
   case MTI_TYPE_RECORD:
    {
     int            i;
     mtiSignalIdT * elem_list;
     mtiInt32T      num_elems;
     elem_list = mti_GetSignalSubelements( sigid, 0 );
     num_elems = mti_GetNumRecordElements( sigtype );
     mti_PrintFormatted( "\n" );
     for ( i = 0; i < num_elems; i++ ) {
      mti_PrintFormatted( "%*c", indent, ' ' );
      printValue( elem_list[i], mti_GetSignalType(elem_list[i]),
                 indent+2 );
     }
     mti_VsimFree( elem_list );
    }
    break;
   case MTI_TYPE_REAL:
    {
     double real_val;
     mti_GetSignalValueIndirect( sigid, &real_val );
     mti_PrintFormatted( "  %g\n", real_val );
    }
    break;
   case MTI_TYPE_TIME:
    {
     mtiTime64T time_val;
     mti_GetSignalValueIndirect( sigid, &time_val );
     mti_PrintFormatted( "  [%d,%d]\n",
                        MTI_TIME64_HI32(time_val),
                        MTI_TIME64_LO32(time_val) );
    }
    break;
   default:
    mti_PrintMessage( "\n" );
    break;
  }
}

static void checkValues( void *inst_info )
{
  instanceInfoT *inst_data = (instanceInfoT *)inst_info;
  signalInfoT   *siginfo;

  mti_PrintFormatted( "Time [%d,%d]:\n", mti_NowUpper(), mti_Now() );

  for ( siginfo = inst_data->sig_info; siginfo; siginfo = siginfo->next ) {
    mti_PrintFormatted( "  Signal %s:", siginfo->name );
    printValue( siginfo->sigid, siginfo->typeid, 4 );
  }

  mti_ScheduleWakeup( inst_data->proc, 5 );
}

static signalInfoT * setupSignal( mtiSignalIdT sigid )
{
  signalInfoT * siginfo;

  siginfo          = (signalInfoT *) mti_Malloc( sizeof(signalInfoT) );
  siginfo->sigid   = sigid;
  siginfo->name    = mti_GetSignalNameIndirect( sigid, 0, 0 );
  siginfo->typeid  = mti_GetSignalType( sigid );
  siginfo->next    = 0;

  return( siginfo );
}

static void initInstance( void )
{
  instanceInfoT * inst_data;
  mtiSignalIdT    sigid;
  signalInfoT   * curr_info;
  signalInfoT   * siginfo;

  inst_data           = mti_Malloc( sizeof(instanceInfoT) );
  inst_data->sig_info = 0;

  for ( sigid = mti_FirstSignal( mti_GetTopRegion() );
        sigid; sigid = mti_NextSignal() ) {
    siginfo = setupSignal( sigid );
    if ( inst_data->sig_info == 0 ) {
        inst_data->sig_info = siginfo;
    }
    else {
        curr_info->next = siginfo;
    }
    curr_info = siginfo;
  }

  inst_data->proc = mti_CreateProcess( "Test Process", checkValues,
                                      (void *)inst_data );
  mti_ScheduleWakeup( inst_data->proc, 6 );
}
void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( initInstance, 0 );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl;";
begin
end a;

library ieee;
use ieee.std_logic_1164.all;

entity top is

  type bitarray  is array( 3 downto 0 ) of bit;
  type intarray  is array( 1 to 3 )     of integer;
  type realarray is array( 1 to 2 )     of real;
  type timearray is array( -1 to 0 )    of time;

  type rectype is record
    a : bit;
    b : integer;
    c : real;
    d : std_logic;
    e : bitarray;
  end record;

end top;

architecture a of top is

  signal bitsig      : bit       := '1';
  signal intsig      : integer   := 21;
  signal realsig     : real      := 16.35;
  signal timesig     : time      := 5 ns;
  signal stdlogicsig : std_logic := 'H';

  signal bitarr      : bitarray  := "0110";
  signal stdlogicarr : std_logic_vector( 1 to 4 ) := "01LH";
  signal intarr      : intarray  := ( 10, 11, 12 );
  signal realarr     : realarray := ( 11.6, 101.22 );
  signal timearr     : timearray := ( 15 ns, 6 ns );

  signal rec         : rectype   := ( '0', 1, 3.7, 'H', "1001" );

  component for_model
  end component;

  for all : for_model use entity work.for_model(a);

begin

  inst1 : for_model;

  bitsig      <= not bitsig after 5 ns;
  intsig      <= intsig + 1 after 5 ns;
  realsig     <= realsig + 1.5 after 5 ns;
  timesig     <= timesig + 1 ns after 5 ns;
  stdlogicsig <= not stdlogicsig after 5 ns;

  bitarr      <= not bitarr after 5 ns;

  intarr(1)   <= intarr(1) + 1 after 5 ns;
  intarr(2)   <= intarr(2) + 1 after 5 ns;
  intarr(3)   <= intarr(3) + 1 after 5 ns;

  realarr(1)  <= realarr(1) + 0.5 after 5 ns;
  realarr(2)  <= realarr(2) + 0.5 after 5 ns;

  timearr(-1) <= timearr(-1) + 1 ns after 5 ns;
  timearr(0)  <= timearr(0)  + 1 ns after 5 ns;

  stdlogicarr <= not stdlogicarr after 5 ns;

  rec.a       <= not rec.a after 5 ns;
  rec.b       <= rec.b + 1 after 5 ns;
  rec.c       <= rec.c + 2.5 after 5 ns;
  rec.d       <= not rec.d after 5 ns;
  rec.e       <= not rec.e after 5 ns;

end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
VSIM 1> run 10
# Time [0,6]:
#   Signal bitsig:  0
#   Signal intsig:  22
#   Signal realsig:  17.85
#   Signal timesig:  [0,6]
#   Signal stdlogicsig:  2
#   Signal bitarr:  '1'  '0'  '0'  '1'
#   Signal stdlogicarr:  '1'  '0'  '1'  '0'
#   Signal intarr:  11  12  13
#   Signal realarr:  12.1  101.72
#   Signal timearr:  [0,16]  [0,7]
#   Signal rec:
#       1
#       2
#       6.2
#       2
#       '0'  '1'  '1'  '0'
VSIM 2> run 10
# Time [0,11]:
#   Signal bitsig:  1
#   Signal intsig:  23
#   Signal realsig:  19.35
#   Signal timesig:  [0,7]
#   Signal stdlogicsig:  3
#   Signal bitarr:  '0'  '1'  '1'  '0'
#   Signal stdlogicarr:  '0'  '1'  '0'  '1'
#   Signal intarr:  12  13  14
#   Signal realarr:  12.6  102.22
#   Signal timearr:  [0,17]  [0,8]
#   Signal rec:
#       0
#       3
#       8.7
#       3
#       '1'  '0'  '0'  '1'
# Time [0,16]:
#   Signal bitsig:  0
#   Signal intsig:  24
#   Signal realsig:  20.85
#   Signal timesig:  [0,8]
#   Signal stdlogicsig:  2
#   Signal bitarr:  '1'  '0'  '0'  '1'
#   Signal stdlogicarr:  '1'  '0'  '1'  '0'
#   Signal intarr:  13  14  15
#   Signal realarr:  13.1  102.72
#   Signal timearr:  [0,18]  [0,9]
#   Signal rec:
#       1
#       4
#       11.2
#       2
#       '0'  '1'  '1'  '0'
VSIM 3> quit 

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