mti_TickLength()

Gets the length of a type.

Syntax

length = mti_TickLength( type_id ) 

Returns

Name	Type	Description
length	mtiInt32T	The length of the range of the specified type; the number of fields for record types; 0 for real and time types

Arguments

Name	Type	Description
type_id	mtiTypeIdT	A handle to a VHDL type

Description

mti_TickLength() returns the value of type'LENGTH (type'HIGH - type'LOW + 1). For record types, the number of fields is returned. For real and time types, 0 is returned.

0 is returned if the length of the range is greater than will fit in a 32-bit integer.

Related functions

mti_TickDir()

mti_TickHigh()

mti_TickLeft()

mti_TickLow()

mti_TickRight()

Example

FLI code

#include <mti.h>

static char * getTypeStr( mtiTypeIdT typeid )
{
  switch ( mti_GetTypeKind( typeid ) ) {
    case MTI_TYPE_SCALAR:    return "Scalar";
    case MTI_TYPE_ARRAY:     return "Array";
    case MTI_TYPE_RECORD:    return "Record";
    case MTI_TYPE_ENUM:      return "Enumeration";
    case MTI_TYPE_PHYSICAL:  return "Physical";
    case MTI_TYPE_REAL:      return "Real";
    case MTI_TYPE_TIME:      return "Time";
    default:                 return "UNKNOWN";
  }
}

static void initInstance( void )
{
  mtiSignalIdT sigid;
  mtiTypeIdT   typeid;

  mti_PrintMessage( "Design Signals:\n" );
  for ( sigid = mti_FirstSignal( mti_GetTopRegion() );
        sigid; sigid = mti_NextSignal() ) {
    typeid = mti_GetSignalType( sigid );
    mti_PrintFormatted( "%14s: type %-12s; length = %d\n",
                       mti_GetSignalName( sigid ), getTypeStr( typeid ),
                       mti_TickLength( typeid ));
  }
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( initInstance, 0 );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl;";
begin
end a;

library ieee;
use ieee.std_logic_1164.all;

entity top is

  type bitarray is array( -2 downto -5 ) of bit;
  type intrange is range 0 to 255;

  type rectype is record
    a : bit;
    b : integer;
    c : bitarray;
  end record;

  type bigtime is range 0 to integer'high
    units
      hour;
      day   = 24 hour;
      week  = 7 day;
      month = 4 week;
      year  = 12 month;
    end units;

end top;

architecture a of top is

  signal bitsig      : bit       := '1';
  signal intsig      : integer   := 42;
  signal physsig     : bigtime   := 3 hour;
  signal realsig     : real      := 10.2;
  signal timesig     : time      := 3 ns;
  signal stdlogicsig : std_logic := 'H';
  signal rangesig    : intrange  := 128;

  signal bitarr      : bitarray := "1100";
  signal stdlogicarr : std_logic_vector( 3 downto 2 ) := "01";
  signal uparray     : bit_vector( 1 to 5 ) := "01010";

  signal rec         : rectype   := ( '0', 0, "1001" );

  component for_model
  end component;

  for all : for_model use entity work.for_model(a);

begin

  inst1 : for_model;

end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
# Design Signals:
#         bitsig: type Enumeration ; length = 2
#         intsig: type Scalar      ; length = 0
#        physsig: type Physical    ; length = 0
#        realsig: type Real        ; length = 0
#        timesig: type Time        ; length = 0
#    stdlogicsig: type Enumeration ; length = 9
#       rangesig: type Scalar      ; length = 256
#         bitarr: type Array       ; length = 4
#    stdlogicarr: type Array       ; length = 2
#        uparray: type Array       ; length = 5
#            rec: type Record      ; length = 3
VSIM 1> quit 

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