mti_GetArrayElementType()

Gets the type of an array type's subelements.

Syntax

elem_type = mti_GetArrayElementType( array_type ) 

Returns

Name	Type	Description
elem_type	mtiTypeIdT	The type ID for the subelements of the array

Arguments

Name	Type	Description
array_type	mtiTypeIdT	A type ID for a VHDL array type

Description

mti_GetArrayElementType() returns a handle to the type ID for the subelements of the specified array type. If the array_type parameter is not a handle to an array type, then NULL is returned.

Related functions

mti_GetTypeKind()

Example

FLI code

#include <mti.h>

static char * getTypeStr( mtiTypeIdT typeid )
{
  char * typestr;

  switch ( mti_GetTypeKind( typeid ) ) {
    case MTI_TYPE_SCALAR:  typestr = "Scalar";  break;
    case MTI_TYPE_ARRAY:  typestr = "Array";  break;
    case MTI_TYPE_RECORD:  typestr = "Record";  break;
    case MTI_TYPE_ENUM:  typestr = "Enum";  break;
    case MTI_TYPE_PHYSICAL:  typestr = "Physical";  break;
    case MTI_TYPE_REAL:  typestr = "Real";  break;
    case MTI_TYPE_ACCESS:  typestr = "Access";  break;
    case MTI_TYPE_FILE:  typestr = "File";  break;
    case MTI_TYPE_TIME:  typestr = "Time";  break;
    default:  typestr = "UNKNOWN";  break;
  }

  return typestr;
}

static void printSignalInfo( mtiSignalIdT sigid, int indent )
{
  char         * fullname;
  int            i;
  mtiInt32T      num_elems;
  mtiSignalIdT * elem_list;
  mtiTypeIdT     sig_type;
  mtiTypeIdT     elem_type;

  fullname = mti_GetSignalNameIndirect( sigid, 0, 0 );
  sig_type = mti_GetSignalType( sigid );

  mti_PrintFormatted( "\n%*cSignal %s is of type %s.\n", indent, ' ',
                   fullname, getTypeStr( sig_type ));
  mti_VsimFree( fullname );

  elem_type = mti_GetArrayElementType( sig_type );
  if ( elem_type ) {
    mti_PrintFormatted( "%*cIts subelements are of type %s.\n",
                       indent, ' ', getTypeStr( elem_type ));
} else {
    if ( mti_GetTypeKind( sig_type ) == MTI_TYPE_RECORD ) {
      mti_PrintFormatted( "%*cThe record subelements are:\n",
                         indent, ' ' );
      elem_list = mti_GetSignalSubelements( sigid, 0 );
      num_elems = mti_GetNumRecordElements( sig_type );
      for ( i = 0; i < num_elems; i++ ) {
        printSignalInfo( elem_list[i], indent+2 );
      }
      mti_VsimFree( elem_list );
    } else {
      mti_PrintFormatted( "%*cThere are no array subelements.\n",
                         indent, ' ' );
    }
  }
}

static void initInstance( void )
{
  mtiSignalIdT sigid;

  for ( sigid = mti_FirstSignal( mti_GetTopRegion() );
        sigid; sigid = mti_NextSignal() ) {
       printSignalInfo( sigid, 1 );
  }
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( initInstance, 0 );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl;";
begin
end a;

library ieee;
use ieee.std_logic_1164.all;

entity top is

  type bitarray  is array( 3 downto 0 ) of bit;
  type intarray  is array( 1 to 3 )     of integer;

  type rectype is record
    a : real;
    b : std_logic;
    c : bitarray;
  end record;

end top;

architecture a of top is

  signal bitsig1      : bit       := '1';
  signal stdlogicsig1 : std_logic := '1';

  signal bitarr1      : bitarray  := "0110";
  signal stdlogicarr1 : std_logic_vector( 1 to 4 ) := "01LH";
  signal intarr1      : intarray  := ( 10, 11, 12 );
  signal strarr1      : string(1 to 5) := "hello";

  signal rec1         : rectype   := ( 1.2, '0', "1001" );

  component for_model
  end component;

  for all : for_model use entity work.for_model(a);

begin

  inst1 : for_model;

  bitsig1      <= not bitsig1 after 5 ns;
  stdlogicsig1 <= not stdlogicsig1 after 5 ns;

  bitarr1      <= not bitarr1 after 5 ns;

  intarr1(1)   <= intarr1(1) + 1 after 5 ns;
  intarr1(2)   <= intarr1(2) + 1 after 5 ns;
  intarr1(3)   <= intarr1(3) + 1 after 5 ns;

  stdlogicarr1 <= not stdlogicarr1 after 5 ns;

  strarr1      <= "there" after 10 ns;

  rec1.a <= rec1.a + 1.1 after 5 ns;
  rec1.b <= not rec1.b after 5 ns;
  rec1.c <= not rec1.c after 5 ns;

end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
# 
#  Signal bitsig1 is of type Enum.
#  There are no array subelements.
# 
#  Signal stdlogicsig1 is of type Enum.
#  There are no array subelements.
# 
#  Signal bitarr1 is of type Array.
#  Its subelements are of type Enum.
# 
#  Signal stdlogicarr1 is of type Array.
#  Its subelements are of type Enum.
# 
#  Signal intarr1 is of type Array.
#  Its subelements are of type Scalar.
# 
#  Signal strarr1 is of type Array.
#  Its subelements are of type Enum.
# 
#  Signal rec1 is of type Record.
#  The record subelements are:
# 
#    Signal rec1.a is of type Real.
#    There are no array subelements.
# 
#    Signal rec1.b is of type Enum.
#    There are no array subelements.
# 
#    Signal rec1.c is of type Array.
#    Its subelements are of type Enum.
VSIM 1> run 10
VSIM 2> quit 

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