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ModelSim

Model Technology Inc.


mti_GetTypeKind()

Gets the kind of a type.

Syntax

type_kind = mti_GetTypeKind( type_id ) 

Returns

Name
Type
Description
type_kind
mtiTypeKindT
The kind of the specified type

Arguments

Name
Type
Description
type_id
mtiTypeIdT
A handle to a VHDL type

Description

mti_GetTypeKind() returns the kind of the specified VHDL type. The returned value is one of the following:

type_kind
VHDL type
MTI_TYPE_SCALAR
Integer
MTI_TYPE_ARRAY
Array
MTI_TYPE_RECORD
Record
MTI_TYPE_ENUM
Enumeration
MTI_TYPE_PHYSICAL
Physical
MTI_TYPE_REAL
Real
MTI_TYPE_ACCESS
Access
MTI_TYPE_FILE
File
MTI_TYPE_TIME
Time

Related functions

None

Example

FLI code

#include <mti.h>

static void printSignalInfo( mtiSignalIdT sigid, int indent )
{
  char         * signame;
  int            i;
  mtiSignalIdT * elem_list;
  mtiTypeIdT     sigtype;

  sigtype = mti_GetSignalType( sigid );
  signame = mti_GetSignalNameIndirect( sigid, 0, 0 );
  mti_PrintFormatted( "%*c%s ", indent, ' ', signame );
  mti_VsimFree( signame );


  switch ( mti_GetTypeKind( sigtype ) ) {
    case MTI_TYPE_SCALAR:
      mti_PrintFormatted( "is of type INTEGER\n" );
      break;
    case MTI_TYPE_ENUM:
      mti_PrintFormatted( "is of type ENUMERATION\n" );
      break;
    case MTI_TYPE_PHYSICAL:
      mti_PrintFormatted( "is of type PHYSICAL\n" );
      break;
    case MTI_TYPE_REAL:
      mti_PrintFormatted( "is of type REAL\n" );
      break;
    case MTI_TYPE_TIME:
      mti_PrintFormatted( "is of type TIME\n" );
      break;
    case MTI_TYPE_ARRAY:
      mti_PrintFormatted( "is of type ARRAY\n" );
      elem_list = mti_GetSignalSubelements( sigid, 0 );
      for ( i = 0; i < mti_TickLength( sigtype ); i++ ) {
        printSignalInfo( elem_list[i], indent+2 );
      }
      mti_VsimFree( elem_list );
      break;
    case MTI_TYPE_RECORD:
      mti_PrintFormatted( "is of type RECORD\n" );
      elem_list = mti_GetSignalSubelements( sigid, 0 );
      for ( i = 0; i < mti_GetNumRecordElements( sigtype ); i++ ) {
        printSignalInfo( elem_list[i], indent+2 );
      }
      mti_VsimFree( elem_list );
      break;
    default:
      mti_PrintFormatted( "is of type UNKNOWN\n" );
      break;
  }
}

void loadDoneCB( void * param )
{
  mtiRegionIdT regid;
  mtiSignalIdT sigid;

  mti_PrintFormatted( "\nSignals:\n" );
  for ( regid = mti_GetTopRegion(); regid; regid = mti_NextRegion(regid) ) {
    for ( sigid = mti_FirstSignal( regid ); sigid;
          sigid = mti_NextSignal()) {
      printSignalInfo( sigid, 2 );
    }
  }
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( loadDoneCB, 0 );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a;

entity top is

  type rectype is record
    a : integer;
    b : bit;
    c : bit_vector( 3 downto 0 );
  end record;

  type a1 is array ( 2 downto 0 ) of bit;
  type a2 is array ( 3 downto 2 ) of a1;

end top;

architecture a of top is

  signal s1 : bit := '0';
  signal s2 : rectype := ( 42, '1', "1100" );
  signal s3 : bit_vector( 7 downto 0 ) := "10001111";
  signal s5 : a2 := ( "101", "011" );
  signal s6 : integer := 42;
  signal s7 : real := 17.8;
  signal s8 : time := 11 ns;

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

begin

  i1 : for_model;

  s1 <= not s1 after 5 ns;

end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
# 
# Signals:
#   s1 is of type ENUMERATION
#   s2 is of type RECORD
#     s2.a is of type INTEGER
#     s2.b is of type ENUMERATION
#     s2.c is of type ARRAY
#       s2.c(3) is of type ENUMERATION
#       s2.c(2) is of type ENUMERATION
#       s2.c(1) is of type ENUMERATION
#       s2.c(0) is of type ENUMERATION
#   s3 is of type ARRAY
#     s3(7) is of type ENUMERATION
#     s3(6) is of type ENUMERATION
#     s3(5) is of type ENUMERATION
#     s3(4) is of type ENUMERATION
#     s3(3) is of type ENUMERATION
#     s3(2) is of type ENUMERATION
#     s3(1) is of type ENUMERATION
#     s3(0) is of type ENUMERATION
#   s5 is of type ARRAY
#     s5(3) is of type ARRAY
#       s5(3)(2) is of type ENUMERATION
#       s5(3)(1) is of type ENUMERATION
#       s5(3)(0) is of type ENUMERATION
#     s5(2) is of type ARRAY
#       s5(2)(2) is of type ENUMERATION
#       s5(2)(1) is of type ENUMERATION
#       s5(2)(0) is of type ENUMERATION
#   s6 is of type INTEGER
#   s7 is of type REAL
#   s8 is of type TIME
VSIM 1> quit 


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