reading a bookVHDL Golden Reference Guide


Doulos’ VHDL Golden Reference Guide is a handy desktop reference for VHDL designers. Serving as both a VHDL reference and an aide de memoire, this small wirebound book contains VHDL syntax, sample code, synthesis caveats and other useful tips. You can obtain a copy of the VHDL Golden Reference Guide from Doulos for the princely sum of £39. Click here to reserve your copy.

The remainder of the text on this page and the related pages is extracted from the VHDL Golden Reference Guide itself (re-formatted for the Web, of course!).

If you are new to VHDL, you should start by reading A Brief Introduction to VHDL.

You’ll also need to refer to the Key to Notation used to define VHDL syntax on the sample pages.

Here’s a selection of sample pages...

...and a taster of the Golden Reference Guide’s contents.

About the VHDL Golden Reference Guide

The VHDL Golden Reference Guide is a compact quick reference guide to the VHDL language, its syntax, semantics, synthesis and application to hardware design.

The VHDL Golden Reference Guide is not intended as a replacement for the IEEE Standard VHDL Language Reference Manual. Unlike that document, the Golden Reference guide does not offer a complete, formal description of VHDL. Rather, it offers answers to the questions most often asked during the practical application of VHDL, in a convenient reference format.

Nor is The VHDL Golden Reference Guide intended to be an introductory tutorial. Information is presented here in a terse reference format, not in the progressive and sympathetic manner necessary to learn a subject as complex as VHDL. However, acknowledging that those already familiar with computer languages may wish to use this guide as a VHDL text book, a brief informal introduction to the subject is given at the start.

The main feature of The VHDL Golden Reference Guide is that it embodies much practical wisdom gathered over many VHDL projects. It does not only provide a handy syntax reference; there are many similar books which perform that task adequately. It also warns you of the most common language errors, gives clues where to look when your code will not compile, alerts you to synthesis issues, and gives advice on improving your coding style.

The VHDL Golden Reference Guide was developed to add value to the Doulos range of VHDL training courses, and also to complement VHDL PaceMaker, the VHDL Computer Based Training package from Doulos.

Using the VHDL Golden Reference Guide

The main body of the guide is organised alphabetically. Each section is indexed by a key term which appears prominently at the top of each page. Often you can find the information you want by flicking through the guide looking for the appropriate key term. If that fails, there is a full index at the back.

Most of the information in the guide is organised around the VHDL syntax headings, but there are additional special sections on Coding Standards, Design Flow, Errors, Reserved Words and VHDL 93, and also listings of the standard packages Standard, TEXTIO, Std_logic_1164 and Numeric_std.

There is a comprehensive index for the VHDL Golden Reference Guide. Bold index entries have corresponding pages in the main alphabetical reference section. The remaining index entries are followed by a list of appropriate page references in the main alphabetical reference section, given in order of importance.

Syntax Summary

For a Syntax Summary of VHDL, click here.

Alphabetic Reference Section

A - E F - P Q - Z
access file qualified expression
aggregate (VHDL) File range
alias floating record
architecture for loop report
array function Reserved Words
assert function call return
attribute generate select
attribute name generic sequential statement
block generic map shared variable
case group signal
Coding Standards if signal assignment
component instantiation standard
concurrent statement integer Std_logic_1164
conditional assignment library string
configuration loop subtype
configuration specification name TextIO
constant new type
data type next type conversion
declaration null use
Design Flow number variable
disconnect Numeric_std variable assignment
entity operator VHDL 93
enumeration package wait
Errors physical while loop
exit port  
expression port map  
  procedure  
  procedure call  
  process  

reference cardVHDL Quick Reference
help iconVHDL FAQ
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