Conditional Assignment

A concurrent statement which assigns one of several expressions to a signal, depending on the values of boolean conditions which are tested in sequence. Equivalent to a process containing an if statement.

Syntax ( Key to Notation )

[Label:] Target <= [Options]
Expression [after TimeExpression] when Condition else
Expression [after TimeExpression] when Condition else
...
Expression [after TimeExpression] [when Condition];

Target = {either} SignalName Aggregate

Options = {either}
guarded
transport
reject TimeExpression inertial

Where

architecture-begin-<HERE>-end
block-begin-<HERE>-end
generate-begin-<HERE>-end

Rules

The reserved word guarded may only appear in a signal assignment within a guarded block. A guarded assignment only executes when the guard expression on the surrounding block is true.
An Expression on the right hand side may be replaced by the reserved word unaffected.

Synthesis

Conditional signal assignments are synthesized to combinational logic. The Expressions on the right hand side are multiplexed onto the Target signal. The resulting logic will be priority encoded, because the Conditions are tested in sequence.

Tips

In VHDL'93, adding a final when part or replacing an expression by unaffected both cause the target signal to retain its value under certain conditions, allowing flipflops and latches to be described as shown below.
Conditional and selected signal assignments are a concise way to describe combinational logic in Register Transfer Level descriptions, although processes can be easier to read and maintain in some cases.
A conditional assignment is a neat way to convert from a Boolean condition to the type Std_logic. See the first example below.

Example