Architecture

Defines the internal view of a block of hardware, i.e. the functionality, behaviour or structure of the hardware. Belongs with an entity, which defines the interface. An entity may have several alternative architectures.

Syntax ( Key to Notation )

architecture ArchitectureName of EntityName is
  Declarations...
begin
  ConcurrentStatements...
end [architecture] [ArchitectureName];

Where

See (VHDL) File

Rules

All the architectures of a particular entity must have different names, but the architectures of two different entities can have the same name.

Gotchas!

It is easy to forget the begin, or put it in the wrong place!

Example

library IEEE;
use IEEE.STD_LOGIC_1164.all;

architecture BENCH of TEST_MUX4 is

  subtype V2 is STD_LOGIC_VECTOR(1 downto 0);

  -- Component declaration...
  component MUX4
    port (SEL, A, B, C, D: in V2;
    F : out V2);
  end component;

  -- Internal signal...
  signal SEL, A, B, C, D, F: V2;

begin

  P: process
  begin
    SEL <= "00";
    wait for 10 NS;
    SEL <= "01";
    wait for 10 NS,
    SEL <= "10";
    wait for 10 NS, 
    SEL <= "11";
    wait for 10 NS;
    wait;
  end process P;

  -- Concurrent assignments...
  A <= "00"; 
  B <= "01";
  C <= "10";
  D <= "11";

  -- Component instantiation...
  M: MUX4 port map (SEL, A, B, C, D, F);

end BENCH;

Architecture

Where

Rules

Gotchas!

Example

See Also