VHDL Model
You will need to fill in the internals of the crs.vhd (Central Reservation Station entity) and drr.vhd (Decode/Rename/Reorder entity) files
- For the first assignment, only need to execute instruction sequences that contain integer add (addreg, addimm) and multiply (multreg, multimm) instructions.
The fetch block now contains the instruction memory and reads instructions from a file
- The default file name is program.txt which should reside in the directory from where you execute the model.
- Can use symbolic links to point this file at different test sequences.