Decode/Rename/Reorder Block (DRR) cont.

• Low Clock Phase (cont)

  • Check if all instructions from last issue were accepted by CRS
    • if not, replace accepted instructions with NOPS and re-issue same values
  • Check if room in ROB
    • if not, issue all NOPs to CRS and don’t increment PC
  • At this point, can accept all instructions from Fetch block; tell Fetch Block to increment PC, place four new instructions in ROB
  • Fetch operands (if available) for each of the 4 instructions
    • If not available, then use ‘renamed’ register number as placeholder
    • Note that this requires DECODING!
    • Operand Fetch MUST BE DONE BEFORE renaming because a source and destination may be same register!
  • Rename destination registers for 4 instructions from
    • Renaming is simply allocating entries in ROB
  • Issue instructions to CRS

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