Decode/Rename/Reorder Block (DRR)

• High Clock Phase

  • Will do ALL work in low clock phase to make modeling easier.

• Low Clock Phase

  • Retire Finished instructions
    • Search Reorder Buffer (ROB); any entry that is marked as finished, write result to register file
    • Note that values written to register file in this high clock can be read in the next low clock phase (flow thru register file).
  • Update ROB with values from result bus
    • An entry that is updated (marked as finished) cannot be retired in this clock cycle, will be retired next clock cycle

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