SuperScalar Abstract Machine

Fe t ch

Fetch model now contains instruction memory.

Ipacket_vec

Rename/Reorder Logic (drr.vhd)

Contains ROB, Register File, Rename mapping table

Epacket

Rpacket_vec

Central Reservation Station

CRSpacket_vec

Integer Unit

Integer Unit

Multiply Unit

Load/Store Unit

Rpacket_vec

latency = 1, rrate = 1

latency = 1, rrate = 1

latency = 3, rrate = 1

latency = 2, rrate = 1

accepted

inc_pc

fetch.vhd

crs.vhd

sint.vhd

sint.vhd

cint.vhd

ldst.vhd

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