Sample test file
# Test basic dependency code # ADDIMM 8 0 0 25 FALSE -- add r8,r0,#25 ; ADDIMM 8 8 0 30 FALSE -- add r8,r8,#30 ; ADDIMM 9 8 0 50 FALSE -- add r9,r8,#50 ; ADDREG 10 9 8 0 TRUE -- add r10,r9,r8 ;
Instruction, case sensitive, name same as VHDL enumerated type names for ‘ops’ type found in abmtypes.vhd .
Dest Reg, Src1 Reg, Src2 Reg, Immediate Field