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Displays information about the peripheral signals used by the design, the source (that is, pin, logic cell, or embedded cell), location, function, whether the signal uses a dedicated clock or peripheral control signal, and the polarity (+ve or -ve) of those signals. This section appears if you specify an ACEX® 1K, APEX™ 20K, APEX™ II, ARM®-based Excalibur™, FLEX 10KE, or MAX® 7000 device for compilation.
For ACEX 1K, FLEX 10KE, and MAX 7000 devices, this section also shows the migration source for the signal if you turn on Base the Pin-Out File (.pin) and floorplan package views on the largest selected SameFrame™ device and select one or more migration devices in the Migration Devices dialog box, which is available from the Device page in the Settings dialog box (Assignments menu).
The following example shows the Peripheral Signals section generated for a sample design:
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