See Also

This section lists the resource usage for each entity in the compilation hierarchy after the synthesis second pass, after the Fitter uses timing information from the first fitting attempt to optimize netlists during synthesis: logic cells, registers, memory bits, macrocells, DSP block sub-blocks, the number of DSP block 9x9, 18x18, and 36x36 multipliers, virtual pins, pins, and logic cell usage (logic cells that only utilize the LUT in the logic cell, logic cells that only use the register, and logic cells that use both register and LUT). The specific resources listed in the Compilation Report may vary depending on the device selected.

The Logic Cells, LUT-Only LCs, Register-Only LCs, and LUT/Register LCs columns list the logic cells used by the design entity (including the design entity) and the number of logic cells (in parenthesis) instantiated by the design entity at that level in the hierarchy.

The following example shows the Resource Utilization by Entity - Second Pass section generated for a sample design. For each entity, the entity's name in the project hierarchy is displayed in the far left column, and the entity's full hierarchical path name is displayed in the far right column.

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